Patents by Inventor Ryo Hirano

Ryo Hirano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210048450
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to a method for manufacturing a semiconductor device of the present invention, the above-described problems can be solved by providing a layout of a TEG electrode pad corresponding to a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 18, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210044610
    Abstract: An anomaly detection device included in a communication network adopting a time-triggered protocol based on a time slot includes: a frame transceiver that receives frames; and an anomaly detector that detects an occurrence of an anomalous frame in accordance with a time slot among a plurality of time slots included in a cycle and the number of repeated cycles of the cycle for each frame. The anomaly detector detects an occurrence of an anomalous frame by verifying a statistic on the frames received while the cycle is repeated a predetermined number of times, which is at least once, against a rule indicating a reference range of the statistic.
    Type: Application
    Filed: October 28, 2020
    Publication date: February 11, 2021
    Inventors: Takeshi KISHIKAWA, Yoshihiro UJIIE, Ryo HIRANO, Tohru WAKABAYASHI
  • Publication number: 20210033642
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of an electrode pad of a TEG to facilitate the evaluation of electrical characteristics. According to the present invention, the above described problem can be solved by arranging a plurality of probes in a fan shape or manufacturing the probes with micro electro mechanical systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: February 4, 2021
    Inventors: Ryo HIRANO, Takayuki MIZUNO, Tomohisa OHTAKI, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210025936
    Abstract: As a semiconductor device is miniaturized, a scribe area on a wafer also tends to decrease. Accordingly, it is necessary to reduce the size of a TEG arranged in the scribe area, and efficiently arrange an electrode pad for probe contact. Therefore, it is necessary to associate probes and the efficient layout of the electrode pad. The purpose of the present invention is to provide a technique for associating probes and the layout of the electrode pads of a TEG so as to facilitate the evaluation of electrical characteristics. According to an evaluation apparatus for a semiconductor device of the present invention, the above described problems can be solved by providing a plurality of probes arranged in a fan shape or probes manufactured by Micro Electro Mechanical Systems (MEMS) technology.
    Type: Application
    Filed: February 6, 2018
    Publication date: January 28, 2021
    Inventors: Tomohisa OHTAKI, Takayuki MIZUNO, Ryo HIRANO, Toru FUJIMURA, Shigehiko KATO, Yasuhiko NARA, Katsuo OHKI, Akira KAGEYAMA, Masaaki KOMORI
  • Publication number: 20210001793
    Abstract: An anomaly handling method in an in-vehicle network includes: transmitting and receiving frames; detecting a frame having an anomaly; and switching, when the anomaly is detected in the detecting, a transmission timing of the frame in which the anomaly is detected. The switching includes changing a switched transmission timing to which the transmission timing is switched, according to predetermined information.
    Type: Application
    Filed: September 24, 2020
    Publication date: January 7, 2021
    Inventors: Yoshihiro UJIIE, Takeshi KISHIKAWA, Ryo HIRANO
  • Patent number: 10886101
    Abstract: A charged particle beam device includes: a charged particle source that emits a charged particle beam; a boosting electrode disposed between the charged particle source and a sample to form a path of the charged particle beam and to accelerate and decelerate the charged particle beam; a first pole piece that covers the boosting electrode; a second pole piece that covers the first pole piece; a first lens coil disposed outside the first pole piece and inside the second pole piece to form a first lens; a second lens coil disposed outside the second pole piece to form a second lens; and a control electrode formed between a distal end portion of the first pole piece and a distal end portion of the second pole piece to control an electric field formed between the sample and the distal end portion of the second pole piece.
    Type: Grant
    Filed: March 29, 2017
    Date of Patent: January 5, 2021
    Assignee: Hitachi High-Tech Corporation
    Inventors: Ryo Hirano, Hideo Morishita, Toshihide Agemura, Junichi Katane, Tsunenori Nomaguchi
  • Publication number: 20200351168
    Abstract: An IDS ECU includes: an anomalous frame detector that detects an anomalous frame; a connector communicator that transmits an anomaly-related request frame to a connector that is a transmitter of the anomalous frame, to request a response from the connector, and receives, from the connector, an anomaly-related response frame generated by the connector based on the anomaly-related request frame and indicating the transmitter; a network anomaly determiner that calculates, from the anomaly-related response frame, the number of anomalous connectors indicating the number of connectors that transmitted the anomaly-related response frame, and determines that an in-vehicle network system is: in a first anomalous state when the number is 0; and in a second anomalous state when the number is not 0; and a network anomaly handler that handles the first or second anomalous state determined by the network anomaly determiner.
    Type: Application
    Filed: July 15, 2020
    Publication date: November 5, 2020
    Inventors: Ryo HIRANO, Takamitsu SASAKI
  • Publication number: 20200251304
    Abstract: The present invention provides a charged particle beam apparatus capable of efficiently reducing the effect of a residual magnetic field when SEM observation is performed. The charged particle beam apparatus according to the present invention includes a first mode for passing a direct current to a second coil after turning off a first coil, and a second mode for passing an alternating current to the second coil after turning off the first coil.
    Type: Application
    Filed: September 4, 2017
    Publication date: August 6, 2020
    Inventors: Ryo HIRANO, Tsunenori NOMAGUCHI, Chisato KAMIYA, Junichi KATANE
  • Publication number: 20200219697
    Abstract: The present invention realizes a composite charged particle beam apparatus capable of suppressing a leakage magnetic field from a pole piece forming an objective lens of an SEM with a simple structure. The charged particle beam apparatus according to the present invention obtains an ion beam observation image while passing a current to a first coil constituting the objective lens, and performs an operation of reducing the image shift by passing a current to a second coil with a plurality of current values, and determines a current to be passed to the second coil based on a difference between the operations.
    Type: Application
    Filed: September 4, 2017
    Publication date: July 9, 2020
    Inventors: Ryo HIRANO, Tsunenori NOMAGUCHI, Chisato KAMIYA, Junichi KATANE
  • Publication number: 20200090903
    Abstract: A charged particle beam device includes: a charged particle source that emits a charged particle beam; a boosting electrode disposed between the charged particle source and a sample to form a path of the charged particle beam and to accelerate and decelerate the charged particle beam; a first pole piece that covers the boosting electrode; a second pole piece that covers the first pole piece; a first lens coil disposed outside the first pole piece and inside the second pole piece to form a first lens; a second lens coil disposed outside the second pole piece to form a second lens; and a control electrode formed between a distal end portion of the first pole piece and a distal end portion of the second pole piece to control an electric field formed between the sample and the distal end portion of the second pole piece.
    Type: Application
    Filed: March 29, 2017
    Publication date: March 19, 2020
    Inventors: Ryo HIRANO, Hideo MORISHITA, Toshihide AGEMURA, Junichi KATANE, Tsunenori NOMAGUCHI
  • Patent number: 9032236
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Grant
    Filed: February 14, 2014
    Date of Patent: May 12, 2015
    Assignee: PS4 Luxco S.A.R.L.
    Inventor: Ryo Hirano
  • Publication number: 20140159778
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Application
    Filed: February 14, 2014
    Publication date: June 12, 2014
    Inventor: Ryo HIRANO
  • Patent number: 8689031
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Grant
    Filed: August 10, 2011
    Date of Patent: April 1, 2014
    Inventor: Ryo Hirano
  • Patent number: 8152164
    Abstract: An image forming apparatus including first and second pairs of rollers for feeding a print medium; the second pair of rollers being disposed downstream from the first pair of rollers; a first detector for detecting the print medium slack in a specified degree by contact with the print medium, the first detector being disposed between the first pair of rollers and the second pair of rollers; a second detector for detecting either the first pair of rollers or the second pair of rollers need a specified value of driving torque; and a controller for controlling either a feeding speed at which the print medium is fed by the first pair of rollers or a feeding speed at which the print medium is fed by the second pair of rollers based on either outputs from the first detector or outputs from the second detector.
    Type: Grant
    Filed: November 22, 2010
    Date of Patent: April 10, 2012
    Assignee: Konica Minolta Business Technologies, Inc.
    Inventors: Ryoichi Yamamoto, Hiroyuki Maeda, Naoki Nonoyama, Kuniaki Ohbayashi, Ryo Hirano
  • Publication number: 20120042188
    Abstract: A semiconductor device includes an internal circuit, a power supply control circuit which controls supply of a power supply to the internal circuit upon receipt of a first control signal, and a control signal generation circuit which outputs the first control signal upon receipt of a second control signal. The control signal generation circuit does not deactivate the first control signal when an inactive period of the second control signal is equal to or less than a first period and deactivates the first control signal when the inactive period of the second control signal is more than the first period.
    Type: Application
    Filed: August 10, 2011
    Publication date: February 16, 2012
    Applicant: ELPIDA MEMORY, INC.
    Inventor: Ryo HIRANO
  • Patent number: 8008055
    Abstract: Polypeptides having an RNase H activity highly useful in genetic engineering; genes encoding these polypeptides; and a process for genetic engineeringly producing these polypeptides.
    Type: Grant
    Filed: August 19, 2008
    Date of Patent: August 30, 2011
    Assignee: Takara Bio Inc.
    Inventors: Takashi Uemori, Yoshimi Sato, Nobuto Koyama, Ryo Hirano, Hikaru Takakura, Hiroshi Kobori, Yuji Hashimoto, Kikyozo Asada, Ikunoshin Kato
  • Publication number: 20110148035
    Abstract: An image forming apparatus comprising a first pair of rollers for feeding a print medium; a second pair of rollers for feeding the print medium, the second pair of rollers being disposed downstream in a print medium feeding direction from the first pair of rollers; a first detector for detecting the print medium slack in a specified degree by contact with the print medium, the first detector being disposed between the first pair of rollers and the second pair of rollers; a second detector for detecting either the first pair of rollers or the second pair of rollers need a specified value of driving torque; and a controller for controlling either a feeding speed at which the print medium is fed by the first pair of rollers or a feeding speed at which the print medium is fed by the second pair of rollers based on either outputs from the first detector or outputs from the second detector.
    Type: Application
    Filed: November 22, 2010
    Publication date: June 23, 2011
    Applicant: Konica Minolta Business Technologies, Inc.
    Inventors: Ryoichi YAMAMOTO, Hiroyuki Maeda, Naoki Nonoyama, Kuniaki Ohbayashi, Ryo Hirano
  • Patent number: 7710142
    Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.
    Type: Grant
    Filed: November 25, 2008
    Date of Patent: May 4, 2010
    Assignee: Elpida Memory, Inc.
    Inventors: Ryo Hirano, Yukihide Suzuki, Hidekazu Egawa
  • Publication number: 20090134892
    Abstract: A semiconductor integrated circuit includes power supply pads of two or more kinds, switches each of which is connected between adjacent two of the power supply pads to allow short-circuiting them, and at least one control line connected to control terminals of the switches according to the kinds of the power supply pads connected to the switches.
    Type: Application
    Filed: November 25, 2008
    Publication date: May 28, 2009
    Applicant: Elpida Memory, Inc.
    Inventors: Ryo HIRANO, Yukihide SUZUKI, Hidekazu EGAWA
  • Publication number: 20090098600
    Abstract: Polypeptides having an RNase H activity highly useful in genetic engineering; genes encoding these polypeptides; and a process for genetic engineeringly producing these polypeptides.
    Type: Application
    Filed: August 19, 2008
    Publication date: April 16, 2009
    Applicant: TAKARA BIO INC.
    Inventors: Takashi Uemori, Yoshimi Sato, Nobuto Koyama, Ryo Hirano, Hikaru Takakura, Hiroshi Kobori, Yuji Hashimoto, Kikyozo Asada, Ikunoshin Kato