Patents by Inventor Ryo MAETA
Ryo MAETA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11469318Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.Type: GrantFiled: March 31, 2020Date of Patent: October 11, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventors: Takeyoshi Nishimura, Ryo Maeta, Isamu Sugai
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Patent number: 11322607Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.Type: GrantFiled: November 20, 2020Date of Patent: May 3, 2022Assignee: FUJI ELECTRIC CO., LTD.Inventor: Ryo Maeta
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Publication number: 20210074847Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.Type: ApplicationFiled: November 20, 2020Publication date: March 11, 2021Applicant: FUJI ELECTRIC CO., LTD.Inventor: Ryo MAETA
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Patent number: 10886397Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.Type: GrantFiled: October 24, 2018Date of Patent: January 5, 2021Assignee: FUJI ELECTRIC CO., LTD.Inventor: Ryo Maeta
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Publication number: 20200365719Abstract: A semiconductor device has an active region through which current passes and an edge termination structure region. On a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. On a surface of the first semiconductor layer, a parallel pn structure including first columns of the first conductivity type and second columns of a second conductivity type disposed to repeatedly alternate one another is provided. The second columns in the active region include first regions and second regions. A distance from the front surface of the semiconductor substrate to a bottom surface of one of the first regions is greater than a distance from the front surface of the semiconductor substrate to a bottom surface of one of the second regions.Type: ApplicationFiled: March 31, 2020Publication date: November 19, 2020Applicant: FUJI ELECTRIC CO., LTD.Inventors: Takeyoshi NISHIMURA, Ryo MAETA, Isamu SUGAI
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Patent number: 10707301Abstract: A semiconductor device has a termination structure region that includes a lower parallel pn structure having lower first-columns of a first conductivity type and lower second-columns of a second conductivity type; a center parallel pn structure having center first-columns of the first conductivity type and first rings of the second conductivity type; an upper parallel pn structure having upper first-columns of the first conductivity type and upper second-columns of the second conductivity type; and an uppermost parallel pn structure having uppermost first-columns of the first conductivity type and second rings of the second conductivity type. The first and second rings are wider than the lower second-columns. An interval between the first rings and between the second rings is wider than an interval between the lower second-columns. Positions of the first rings differ from positions of the second rings, along a direction parallel to a front surface of the semiconductor device.Type: GrantFiled: May 30, 2018Date of Patent: July 7, 2020Assignee: FUJI ELECTRIC CO., LTD.Inventor: Ryo Maeta
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Publication number: 20190181260Abstract: A semiconductor device has an active region through which current flows and a termination structure region. At a front surface of a semiconductor substrate of a first conductivity type, a first semiconductor layer of the first conductivity type is provided. At a surface of the first semiconductor layer, a lower parallel pn structure is provided. At a surface of the lower parallel pn structure, an upper parallel pn structure is provided in the termination structure region and a first semiconductor region of a second conductivity type is provided in the active region. A width of an upper second column is wider than a width of a lower second column. An interval between the upper second columns is wider than an interval between the lower second columns. A thickness of the upper second column is thicker than a thickness of the first semiconductor region.Type: ApplicationFiled: October 24, 2018Publication date: June 13, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventor: Ryo Maeta
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Publication number: 20190027555Abstract: A semiconductor device has a termination structure region that includes a lower parallel pn structure having lower first-columns of a first conductivity type and lower second-columns of a second conductivity type; a center parallel pn structure having center first-columns of the first conductivity type and first rings of the second conductivity type; an upper parallel pn structure having upper first-columns of the first conductivity type and upper second-columns of the second conductivity type; and an uppermost parallel pn structure having uppermost first-columns of the first conductivity type and second rings of the second conductivity type. The first and second rings are wider than the lower second-columns. An interval between the first rings and between the second rings is wider than an interval between the lower second-columns. Positions of the first rings differ from positions of the second rings, along a direction parallel to a front surface of the semiconductor device.Type: ApplicationFiled: May 30, 2018Publication date: January 24, 2019Applicant: FUJI ELECTRIC CO., LTD.Inventor: Ryo MAETA
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Patent number: 10090408Abstract: A SJ-MOSFET includes a parallel pn layer in which an n-type drift region and a p-type partition region are alternately arranged repeatedly along a direction parallel to a base main-surface. The n-type drift region and the p-type partition region have total impurity amounts that are roughly the same and widths that are basically constant over an entire depth direction. The n-type drift region is configured to have an n-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by ?Cnx. The p-type partition region is configured to have a p-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by ?Cph, and an impurity concentration of part of the portion on the source-side is relatively low.Type: GrantFiled: August 1, 2017Date of Patent: October 2, 2018Assignee: FUJI ELECTRIC CO., LTD.Inventors: Ryo Maeta, Toshiaki Sakata, Shunji Takenoiri
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Publication number: 20180076315Abstract: A SJ-MOSFET includes a parallel pn layer in which an n-type drift region and a p-type partition region are alternately arranged repeatedly along a direction parallel to a base main-surface. The n-type drift region and the p-type partition region have total impurity amounts that are roughly the same and widths that are basically constant over an entire depth direction. The n-type drift region is configured to have an n-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by ?Cnx. The p-type partition region is configured to have a p-type impurity concentration profile in which an impurity concentration of a portion on the drain-side is higher than an impurity concentration of a portion on the source-side by ?Cph, and an impurity concentration of part of the portion on the source-side is relatively low.Type: ApplicationFiled: August 1, 2017Publication date: March 15, 2018Applicant: FUJI ELECTRIC CO., LTD.Inventors: Ryo MAETA, Toshiaki SAKATA, Shunji TAKENOIRI