Abstract: A liquid crystal panel includes: a display region, and a picture-frame region provided around the display region; and a first substrate, a second substrate disposed across from the first substrate, and a liquid crystal layer and a plurality of spacers disposed between the first substrate and the second substrate. Either the first substrate or the second substrate has a picture-frame wire disposed in the picture-frame region, and the first substrate has: a transparent conductive layer; and a metal wire extending from the picture-frame wire toward the display region, and electrically connected to the transparent conductive layer in regions overlapping with the plurality of spacers in plan view.

Abstract: The present application discloses a current-driven display device employing an internal compensation method capable of achieving high-resolution of the display image while suppressing a reduction in the yield of manufacturing, the deterioration in display quality, an increase in the circuit amount. In a pixel circuit of an organic EL display device, a voltage of the gate terminal of a drive transistor is initialized before the voltage of a data signal line is written into a holding capacitor via the drive transistor in a diode-connected state. At this time, a current flows from the holding capacitor connected to the gate terminal of the drive transistor to an initialization voltage line via a threshold compensation transistor, a second light emission control transistor, and a display element initialization transistor, and the voltage of the gate terminal is initialized.

Abstract: A display device provided with a light-emitting element layer in which a plurality of light-emitting elements each including a first electrode, a function layer, and a second electrode are formed. An auxiliary electrode is provided on a lower side of an edge cover film covering an edge of the first electrode, a function layer includes a common function layer common to the plurality of light-emitting elements and individual function layers, each of which corresponding to each of the plurality of light-emitting elements, the common function layer includes an upper common function layer provided between the light-emitting layers included in the individual function layers, respectively, and the second electrode, and a film thickness of the auxiliary electrode is greater than a film thickness of the upper common function layer.

Abstract: A pixel circuit of a display device includes: a light-emitting element; a drive transistor; a write control transistor having one conductive terminal connected to a data line and a control terminal connected to a scanning line; a first capacitor provided between a control terminal of the drive transistor and a conductive terminal of the drive transistor on the light-emitting element side; a second capacitor provided between another conductive terminal of the write control transistor and the control terminal of the drive transistor; and a mode selection circuit provided in parallel to the second capacitor and configured to cause a short-circuit and an open-circuit between electrodes of the second capacitor in accordance with a voltage of a mode selection line. Accordingly, a display device capable of easily performing gradation control is provided.

Abstract: When a current-driven display device with an internal compensation method operates in a pause driving mode, a non-light emission period according to a light emission duty is provided in both a refresh frame period and a non-refresh frame period, and an on-bias applying period for applying on-bias to a drive transistor in a pixel circuit is provided in both the non-light emission periods. In the non-light emission period in the refresh frame period, an on-bias applying period is provided in a period from when data writing with threshold compensation is performed to when the light emission period starts. Thus, even when the light emission duty is low, the difference in the stress state of the drive transistor between the refresh frame period and the non-refresh frame period is reduced.

Abstract: A display device is implemented that can reduce power consumption over a known example while preventing occurrence of black floating. The voltage value of a low-level power supply voltage ELVSS provided to a pixel circuit is set to a higher value in a pause driving period than in a normal driving period. Upon writing a data voltage, an anode initialization period for initializing an anode voltage of an organic EL element is provided. In this regard, an anode initialization period in the pause driving period is made longer than an anode initialization period in the normal driving period. To implement this, for example, a write frequency of a data voltage is made lower in the pause driving period than in the normal driving period.

Abstract: The present application discloses a current-driven display device employing an internal compensation method capable of achieving high-resolution of the display image while suppressing a reduction in the yield of manufacturing, the deterioration in display quality, an increase in the circuit amount. In a pixel circuit of an organic EL display device, a voltage of the gate terminal of a drive transistor is initialized before the voltage of a data signal line is written into a holding capacitor via the drive transistor in a diode-connected state. At this time, a current flows from the holding capacitor connected to the gate terminal of the drive transistor to an initialization voltage line via a threshold compensation transistor, a second light emission control transistor, and a display element initialization transistor, and the voltage Vg of the gate terminal is initialized.

Abstract: In a pixel circuit of a display device in which display luminance is controlled by a holding voltage of the capacitor Cst, a gate terminal of a drive transistor M1 is connected to a source terminal of the drive transistor M1 via a capacitance selection transistor M3 and the holding capacitor Cst and is also connected to the source terminal via only an auxiliary writing capacitor Cwa. During a data writing period Tw, the capacitance selection transistor M3 is turned off, and data voltage is provided from a data signal line Dj to the auxiliary writing capacitor Cwa via a writing control transistor M2. Thereafter, the writing control transistor M2 is turned off, the capacitance selection transistor M3 is turned on, so that charges are redistributed between the auxiliary writing capacitor Cwa and the holding capacitor Cst, whereby a driving holding voltage is determined.

Abstract: Provided are a liquid crystal panel capable of sufficiently reducing noise without an increase in load on the system, and an active retarder for 3D image display and a display device each including the liquid crystal panel. The liquid crystal panel includes: pixels adjacent to one another; a pair of substrates; pixel electrodes corresponding to the respective pixels; common electrodes overlapping the respective pixel electrodes; a liquid crystal layer; and an input unit. The pixel electrodes, the common electrodes, and the liquid crystal layer are disposed between the pair of substrates. The common electrodes are adjacent to one another across an aperture in a plan view. The aperture overlaps a boundary between the pixel electrodes. The input unit is configured to input a same signal to the common electrodes.

Abstract: A display device is implemented that can reduce power consumption over a known example while preventing occurrence of black floating. The voltage value of a low-level power supply voltage ELVSS provided to a pixel circuit is set to a higher value in a pause driving period than in a normal driving period. Upon writing a data voltage, an anode initialization period for initializing an anode voltage of an organic EL element is provided. In this regard, an anode initialization period in the pause driving period is made longer than an anode initialization period in the normal driving period. To implement this, for example, a write frequency of a data voltage is made lower in the pause driving period than in the normal driving period.

Abstract: A display device includes a display control circuit configured to control a data-side drive circuit and a scanning-side drive circuit such that a drive period and a pause period alternate between one another. The display control circuit, in the pause period, such that voltage of corresponding data signal line is applied to first conduction terminal of drive transistor as bias voltage when light emission control transistor is in an off state and current corresponding to holding voltage of holding capacitor flows through display element when light emission control transistor is in an on state, causes the data-side drive circuit to output the bias voltage and apply the bias voltage to data signal lines and causes the scanning-side drive circuit to stop driving first scanning signal lines and selectively drive second scanning signal lines and selectively make light emission control lines inactive.

Abstract: A display device includes an active matrix substrate including a plurality of pixels and a driver unit. The driver unit includes a flexible substrate, a first wiring pattern disposed on the flexible substrate, a demultiplexer circuit or a multiplexer circuit supported by the flexible substrate and connected to the first wiring pattern, and a source driver IC supported by the flexible substrate and connected to the first wiring pattern. The driver unit is connected to a display panel, and a TFT of the plurality of pixels and a TFT of the demultiplexer circuit or the multiplexer circuit have semiconductors different from each other.

Abstract: The present application discloses a display device capable of preventing a black display defect with a pixel circuit used therein in which P-type and N-type transistors are mixed. Provided is a pixel circuit including an organic EL element, a holding capacitor, a P-type drive transistor, a P-type writing control transistor, an N-type threshold compensation transistor, and the like, wherein during a data writing period, the voltage of a data signal line is written to the holding capacitor via the writing control transistor in ON state and the drive transistor brought into a diode-connected state by the threshold compensation transistor in ON state. A capacitance is provided between a first scanning signal line connected to a gate terminal of the writing control transistor and a gate terminal of the drive transistor.

Abstract: To make a frame size of a display device having an external compensation function smaller than those of the known display devices. Each of a plurality of unit circuits configuring a gate driver includes a first output control transistor including a second conduction terminal connected to a first output terminal-connected to another unit circuit and a control terminal connected to a first internal node, a second output control transistor including a second conduction terminal connected to a second output terminal configured to output an on level signal for at least a part of a monitoring period and a control terminal connected to a second internal node, and an output circuit control transistor including a first conduction terminal connected to the first internal node and a second conduction terminal connected to the second internal node. A potential to be applied to a control terminal of the output circuit control transistor is switched between a potential of a high level and a potential of a low level.

Abstract: A pixel circuit of a display device includes: a light-emitting element; a drive transistor; a write control transistor having one conductive terminal connected to a data line and a control terminal connected to a scanning line; a first capacitor provided between a control terminal of the drive transistor and a conductive terminal of the drive transistor on the light-emitting element side; a second capacitor provided between another conductive terminal of the write control transistor and the control terminal of the drive transistor; and a mode selection circuit provided in parallel to the second capacitor and configured to cause a short-circuit and an open-circuit between electrodes of the second capacitor in accordance with a voltage of a mode selection line. Accordingly, a display device capable of easily performing gradation control is provided.

Abstract: A display device includes a first substrate, a second substrate, a first electrically conductive portion and a second electrically conductive portion disposed between the first substrate and the second substrates. The first substrate includes a first line, a second line, a first connection electrode projecting from the first line toward the second line, and a second connection electrode projecting from the second line toward the first line. The second substrate includes a first electrode, a third connection electrode electrically connected to the first electrode and disposed to overlap the first connection electrode, a second electrode, and a fourth connection electrode electrically connected to the second electrode and disposed to overlap the second connection electrode. The first electrically conductive portion overlaps and contacts the first connection electrode and the third connection electrode.

Abstract: A display device includes a display control circuit configured to control a data-side drive circuit and a scanning-side drive circuit such that a drive period and a pause period alternate between one another. The display control circuit, in the pause period, such that voltage of corresponding data signal line is applied to first conduction terminal of drive transistor as bias voltage when light emission control transistor is in an off state and current corresponding to holding voltage of holding capacitor flows through display element when light emission control transistor is in an on state, causes the data-side drive circuit to output the bias voltage and apply the bias voltage to data signal lines and causes the scanning-side drive circuit to stop driving first scanning signal lines and selectively drive second scanning signal lines and selectively make light emission control lines inactive.

Abstract: A display device includes a first substrate, a second substrate, a first electrically conductive portion and a second electrically conductive portion disposed between the first substrate and the second substrates. The first substrate includes a first line, a second line, a first connection electrode projecting from the first line toward the second line, and a second connection electrode projecting from the second line toward the first line. The second substrate includes a first electrode, a third connection electrode electrically connected to the first electrode and disposed to overlap the first connection electrode, a second electrode, and a fourth connection electrode electrically connected to the second electrode and disposed to overlap the second connection electrode. The first electrically conductive portion overlaps and contacts the first connection electrode and the third connection electrode.

Abstract: A display device includes: a display region; and a frame region disposed around the display region. The frame region partly includes a terminal section, wherein the frame region includes a main-power-source-voltage stem wire and an auxiliary-power-source-voltage stem wire. The frame region includes a first frame region having the terminal section, and a second frame region located opposite the first frame region with reference to the display region. The main-power-source-voltage stem wire has a potential different from a potential of the auxiliary-power-source-voltage stem wire, and the main-power-source-voltage stem wire and the auxiliary-power-source-voltage stem wire are electrically connected together.

Abstract: In a pixel circuit of a display device in which display luminance is controlled by a holding voltage of the capacitor Cst, a gate terminal of a drive transistor M1 is connected to a source terminal of the drive transistor M1 via a capacitance selection transistor M3 and the holding capacitor Cst and is also connected to the source terminal via only an auxiliary writing capacitor Cwa. During a data writing period Tw, the capacitance selection transistor M3 is turned off, and data voltage is provided from a data signal line Dj to the auxiliary writing capacitor Cwa via a writing control transistor M2. Thereafter, the writing control transistor M2 is turned off, the capacitance selection transistor M3 is turned on, so that charges are redistributed between the auxiliary writing capacitor Cwa and the holding capacitor Cst, whereby a driving holding voltage is determined.