Abstract: A plurality of DMA transfer request signals corresponding to a plurality of channels are received and held in a plurality of transfer request holding circuits respectively. A plurality of DMA transfers are assigned to the DMA transfer request signals respectively in a channel transfer request arbitrating circuit according to priorities set in advance for the DMA transfer request signals, and the DMA transfers for the DMA transfer request signals are performed in the order of lowering the priority. Also, a transfer waiting time period from the reception of one DMA transfer request signal to the assignment of the DMA transfer is measured in a transfer waiting time counter for each DMA transfer request signal, and the transfer waiting times are, for example, stored in a storing circuit and are selectively read out.

Abstract: In a read only memory, compression data of original data are stored in a storage unit, a read address which is given from the outside in order to read original data is converted into a storage address of the compression data in the storage unit which corresponds to the original data, the compression data which is read out in accordance with the converted storage address is expanded to restore the original data, and the restored original data is read out to the outside. In order to make it difficult for an unauthorized person to use the ROM, dummy address conversion data are mixed with address conversion data.

Abstract: Data is transferred directly from a source register in a register file connected to a data bus from a destination register in the register file, through a read data latch, a data bus bypass mechanism, and a write data latch. Since the data bus is bypassed, the update of a data pointer is possible concurrently with the transfer of data between the source register and the destination register.