Patents by Inventor Ryohei Kitao

Ryohei Kitao has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210087669
    Abstract: A film forming apparatus according to an embodiment includes: a process chamber forming a film on a substrate; an abatement device detoxifying a first exhaust gas exhausted from the process chamber; a first supply pipe for supplying a gas containing water to the process chamber; a first vacuum pump provided in a first flow path of the first exhaust gas between the process chamber and the abatement device; a second vacuum pump provided in the first flow path between the first vacuum pump and the abatement device; and a first detector provided in the first flow path between the second vacuum pump and the abatement device and capable of detecting a hydrogenated gas.
    Type: Application
    Filed: August 26, 2020
    Publication date: March 25, 2021
    Applicant: Kioxia Corporation
    Inventors: Yuta KONNO, Toshihiko Nagase, Atsuko Sakata, Kohei Nagata, Ryohei Kitao, Akifumi Gawase, Takeshi Iwasaki
  • Patent number: 10892300
    Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).
    Type: Grant
    Filed: September 13, 2019
    Date of Patent: January 12, 2021
    Assignee: Toshiba Memory Corporation
    Inventors: Takanori Usami, Takeshi Ishizaki, Ryohei Kitao, Katsuyoshi Komatsu, Takeshi Iwasaki, Atsuko Sakata
  • Publication number: 20200286954
    Abstract: A storage device according to embodiments includes a first conductive layer; a second conductive layer; a resistance change element provided between the first conductive layer and the second conductive layer; and an intermediate layer provided in any one of a position between the resistance change element and the first conductive layer and a position between the resistance change element and the second conductive layer, the intermediate layer containing at least one element of silicon (Si) and germanium (Ge), tellurium (Te), and aluminum (Al).
    Type: Application
    Filed: September 13, 2019
    Publication date: September 10, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Takanori USAMI, Takeshi ISHIZAKI, Ryohei KITAO, Katsuyoshi KOMATSU, Takeshi IWASAKI, Atsuko SAKATA
  • Publication number: 20200127007
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: December 18, 2019
    Publication date: April 23, 2020
    Applicant: TOSHIBA MEMORY CORPORATION
    Inventors: Ryohei KITAO, Atsuko SAKATA, Takeshi ISHIZAKI, Satoshi WAKATSUKI, Shinichi NAKAO, Shunsuke OCHIAI, Kei WATANABE
  • Patent number: 10541250
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Grant
    Filed: June 28, 2016
    Date of Patent: January 21, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Ryohei Kitao, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Publication number: 20180277667
    Abstract: A semiconductor device includes first and second electrodes, first semiconductor region of first conductivity type between the first and second electrodes, a second semiconductor region of second conductivity type between the first semiconductor region and the first electrode, a third semiconductor region of the second conductivity type between the first semiconductor region and the second electrode, a fourth semiconductor region of the first conductivity type between the third semiconductor region and the second electrode, a plurality of third electrodes between the second electrode and the first semiconductor region, wherein a gate insulating film is between each third electrode and the third semiconductor region, a fourth electrode extending between the third semiconductor region and the second electrode and electrically connected to the third semiconductor region and the second electrode, and a first insulating film between the second and electrodes.
    Type: Application
    Filed: August 29, 2017
    Publication date: September 27, 2018
    Inventors: Hideki SEKIGUCHI, Keiko KAWAMURA, Kaori FUSE, Akira KOMATSU, Ryohei KITAO, Satoshi WAKATSUKI, Atsuko SAKATA, Koichi KUBO
  • Patent number: 9779992
    Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.
    Type: Grant
    Filed: February 2, 2016
    Date of Patent: October 3, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryohei Kitao, Yasuaki Tsuchiya
  • Publication number: 20170186766
    Abstract: A method of manufacturing a semiconductor device according to one embodiment includes forming a first film including a first metal above a processing target member. The method includes forming a second film including two or more types of element out of a second metal, carbon, and boron above the first film. The method includes forming a third film including the first metal above the second film. The method includes forming a mask film by providing an opening part to a stacked film including the first film, the second film and the third film. The method includes processing the processing target member by performing etching using the mask film as a mask.
    Type: Application
    Filed: June 28, 2016
    Publication date: June 29, 2017
    Inventors: Ryohei KITAO, Atsuko Sakata, Takeshi Ishizaki, Satoshi Wakatsuki, Shinichi Nakao, Shunsuke Ochiai, Kei Watanabe
  • Patent number: 9685517
    Abstract: A silicon substrate is restrained from being warped. A substrate is formed by use of a silicon substrate. The substrate has a first surface and a second surface opposite to each other. A metal film is formed over the first surface. An interconnection layer is formed over the second surface. The metal film has a face centered cubic lattice structure. When the metal film is measured by XRD (X-ray diffraction), the [111] orientation intensity A(111), the [220] orientation intensity A(220) and the [311] orientation intensity A(311) of the metal film satisfy the following: A(111)/{A(220)+A(311)}?10.
    Type: Grant
    Filed: June 5, 2015
    Date of Patent: June 20, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventor: Ryohei Kitao
  • Patent number: 9673217
    Abstract: According to one embodiment, a semiconductor device includes a stacked body, a semiconductor body, and a stacked film. The stacked body includes a plurality of tungsten layers and a plurality of alloy layers of tungsten and molybdenum. At least portions of the tungsten layers are stacked with an air gap interposed. The alloy layers are provided on surfaces of the tungsten layers opposing the air gap. The semiconductor body extends in a stacking direction through the stacked body. The stacked film is provided between the semiconductor body and the tungsten layers. The stacked film includes a charge storage portion.
    Type: Grant
    Filed: September 7, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Atsuko Sakata, Yohei Sato, Yasuhito Yoshimizu, Satoshi Wakatsuki, Takeshi Ishizaki, Masayuki Kitamura, Daisuke Ikeno, Tomotaka Ariga, Junichi Wada, Hiroshi Tomita, Hisashi Okuchi, Ryohei Kitao, Toshiyuki Sasaki, Kazuhito Furumoto
  • Publication number: 20160148841
    Abstract: A method of manufacturing a semiconductor device includes forming a first via having a first diameter in a first main surface of a semiconductor substrate having a first thickness, after forming a first insulating film on a bottom surface and a side surface of the first via, forming a first through electrode inside the first via a first barrier metal film, after forming the first through electrode, processing the semiconductor substrate from a second main surface on an opposite side of the first main surface to reduce the first thickness of the semiconductor substrate to a second thickness thinner than the first thickness, after processing the semiconductor substrate, forming a third insulating film on the second main surface of the semiconductor substrate, and after forming the third insulating film, sequentially processing the third insulating film and the semiconductor substrate.
    Type: Application
    Filed: February 2, 2016
    Publication date: May 26, 2016
    Inventors: RYOHEI KITAO, Yasuaki Tsuchiya
  • Patent number: 9275935
    Abstract: Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view.
    Type: Grant
    Filed: August 7, 2013
    Date of Patent: March 1, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Ryohei Kitao, Yasuaki Tsuchiya
  • Publication number: 20150357424
    Abstract: A silicon substrate is restrained from being warped. A substrate is formed by use of a silicon substrate. The substrate has a first surface and a second surface opposite to each other. A metal film is formed over the first surface. An interconnection layer is formed over the second surface. The metal film has a face centered cubic lattice structure. When the metal film is measured by XRD (X-ray diffraction), the [111] orientation intensity A(111), the [220] orientation intensity A(220) and the [311] orientation intensity A(311) of the metal film satisfy the following: A(111)/{A(220)+A(311)}?10.
    Type: Application
    Filed: June 5, 2015
    Publication date: December 10, 2015
    Inventor: Ryohei KITAO
  • Publication number: 20140061940
    Abstract: Technology that achieves high integration of a semiconductor device employing TSV technology is provided. A through electrode is configured by a small-diameter through electrode having a first diameter and being formed on a main surface side of a semiconductor wafer, and a large-diameter through electrode having a second diameter larger than the above-described first diameter and being formed on a back surface side of the semiconductor wafer, and the small-diameter through electrode is arranged inside the large-diameter through electrode in a planar view so that a center position of the small-diameter through electrode and a center position of the large-diameter through electrode do not overlap with each other in the planar view.
    Type: Application
    Filed: August 7, 2013
    Publication date: March 6, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Ryohei KITAO, Yasuaki Tsuchiya
  • Patent number: 8038864
    Abstract: A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr=S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.
    Type: Grant
    Filed: July 27, 2007
    Date of Patent: October 18, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Koji Arita, Ryohei Kitao
  • Publication number: 20110227224
    Abstract: A semiconductor device includes an interlayer insulating film formed over a semiconductor substrate, a through hole formed in the interlayer insulating film, a Cu film filling the through hole, and a metal-containing base film formed on the sidewall inside the through hole and serving as a base of the Cu film. The metal-containing base film has a metal nitride layer at the interface with the Cu film in a first region including a sidewall area adjacent to the opening of the through hole. In a second region including a sidewall area nearer to the semiconductor substrate than is the first region, the metal-containing base film has a metal layer at the interface with the Cu film. The deposition rate of the Cu film on the surface of the metal layer is greater than the deposition rate of the Cu film on the surface of the metal nitride layer.
    Type: Application
    Filed: February 16, 2011
    Publication date: September 22, 2011
    Applicant: Renesas Electronics Corporation
    Inventor: Ryohei Kitao
  • Patent number: 7833901
    Abstract: In a method of manufacturing a semiconductor device where at least one insulating layer structure having a metal wiring constitution is formed to thereby construct a multi-layered wiring arrangement, a first SiOCH layer is produced. Then, a surface section of the first SiOCH layer is treated to change the surface section of the first SiOCH layer to a second SiOCH layer which features a carbon (C) density lower than that of the first SiOCH layer, a hydrogen (H) density lower than that of the first SiOCH layer and an oxygen (O) density higher than that of the first SiOCH layer. Finally, a silicon dioxide (SiO2) layer is formed on the second SiOCH layer.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: November 16, 2010
    Assignee: NEC Electronics Corporation
    Inventors: Koichi Ohto, Tatsuya Usami, Noboru Morita, Sadayuki Ohnishi, Koji Arita, Ryohei Kitao, Yoichi Sasaki
  • Patent number: 7563705
    Abstract: A manufacturing method of a semiconductor device including a step of forming a via hole in an insulation layer including an organic low dielectric film, such as MSQ, SiC, and SiCN, and then embedding a wiring material in the via hole through a barrier metal. According to this method, a plasma treatment is performed after the via hole is formed and before the barrier metal is deposited, using a He/H2 gas capable of replacing groups (methyl groups) made of organic constituents and covering the surface of the exposed organic low dielectric film (MSQ) with hydrogen, or a He gas capable decomposing the groups (methyl groups) without removing organic low dielectric molecules. As a result, the surface of the low dielectric film (MSQ) is reformed to be hydrophilic and adhesion to the barrier metal is hence improved, thereby making it possible to prevent the occurrence of separation of the barrier metal and scratches.
    Type: Grant
    Filed: February 23, 2006
    Date of Patent: July 21, 2009
    Assignee: NEC Electronics Corporation
    Inventors: Takashi Tonegawa, Koji Arita, Tatsuya Usami, Noboru Morita, Koichi Ohto, Yoichi Sasaki, Sadayuki Ohnishi, Ryohei Kitao
  • Publication number: 20080023335
    Abstract: A method of fabricating a semiconductor device of the invention includes a plating process of filling a plurality of recesses provided to an insulating film formed on a substrate with an electro-conductive material, wherein the plating process includes a process step (S104) of performing the plating with a first current density which was obtained by correcting a predetermined first reference current density based on ratio of surface area Sr?S1/S2 of a first surface area S1 over the entire surface of the substrate which includes the area of side walls of the plurality of recesses over the entire surface of the semiconductor substrate, and a second surface area S2 over the entire surface of the substrate which does not include the area of side walls of the plurality of recesses, when fine recesses not larger than a predetermined width, out of all of the plurality of recesses, are filled with the electro-conductive material.
    Type: Application
    Filed: July 27, 2007
    Publication date: January 31, 2008
    Applicant: NEC ELECTRONICS CORPORATION
    Inventors: Koji ARITA, Ryohei KITAO
  • Patent number: 7229916
    Abstract: A method of manufacturing a semiconductor device is to be provided, which improves filling performance of a conductive layer to be formed by an electrolytic plating process in an interconnect trench or a via hole, and achieves a higher in-plane uniformity in bottom-up performance. An electrolytic plating process to fill with a conductive layer at least one of an interconnect trench and a via hole formed in a dielectric layer on a semiconductor substrate includes a first step of executing a plating operation under a predetermined integrated current density, which is a product of a current density representing a current value supplied per unit area of a plating solution containing a material which constitutes the conductive layer and a plating time, and a second step of executing a plating operation under a lower current density than that of the first step.
    Type: Grant
    Filed: July 16, 2004
    Date of Patent: June 12, 2007
    Assignee: NEC Electronics Corporation
    Inventors: Ryohei Kitao, Koji Arita