Patents by Inventor Ryohei Okazaki

Ryohei Okazaki has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11210101
    Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: December 28, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Sota Sakashita, Atushi Fusejima
  • Publication number: 20210318868
    Abstract: An arithmetic processing device includes: a decoder configured to write an immediate value to a register in a case where an instruction to be executed is an instruction not involving data reading from the register; and a processor configured to read data from the register and write a computing result based on the read data to the register in a case where an instruction to be executed by the decoder is an instruction involving data reading from the register.
    Type: Application
    Filed: February 3, 2021
    Publication date: October 14, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Publication number: 20210318854
    Abstract: An arithmetic processing apparatus includes two instruction decoders. A first decoder processes instructions in a single cycle, while a second decoder processes instructions in a plurality of cycles. The apparatus further includes a determination circuit that causes the first decoder to process an instruction to be processed when the instruction to be processed is a specific instruction and there is no previous instruction being processed, and causes the second decoder to process the instruction to be processed when the instruction to be processed is not the specific instruction or there is a previous instruction being processed.
    Type: Application
    Filed: February 23, 2021
    Publication date: October 14, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 11080063
    Abstract: A processing device includes an instruction extractor that extracts target instructions intended for a loop process that is repeatedly performed, from instructions decoded by an instruction decoder, and a loop buffer including entries where each of the target instructions extracted by an instruction extractor are stored. An instruction processor stores a target instruction into one of the entries of the loop buffer, and combines target instructions into one target instruction in a case where resources of an instruction execution circuit used by the target instructions do not overlap, to store the one instruction in one of the entries of the loop buffer, and a selector selects the instruction output from the instruction decoder or the target instruction output from the loop buffer, and outputs the selected instruction to the instruction execution circuit.
    Type: Grant
    Filed: October 28, 2019
    Date of Patent: August 3, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 10983790
    Abstract: An arithmetic processing unit includes an instruction decoder, first to fourth reservation stations, first and second computing units, first and second load-store units, and an allocation unit. The allocation unit, when the execution instruction is a first instruction that is executable in first and second computing units but not executable in first and second load-store units, allocates the first instruction to first or second reservation station based on a first allocation table, and when the execution instruction is a second instruction that is executable in the first and second load-store units but not executable in the first and second computing units, allocates the second instruction to third or fourth reservation station based on a second allocation table.
    Type: Grant
    Filed: March 22, 2019
    Date of Patent: April 20, 2021
    Assignee: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Publication number: 20210089302
    Abstract: An arithmetic processing unit includes an instruction decoder, first to fourth reservation stations, first and second computing units, first and second load-store units, and an allocation unit. The allocation unit, when the execution instruction is a first instruction that is executable in first and second computing units but not executable in first and second load-store units, allocates the first instruction to first or second reservation station based on a first allocation table, and when the execution instruction is a second instruction that is executable in the first and second load-store units but not executable in the first and second computing units, allocates the second instruction to third or fourth reservation station based on a second allocation table.
    Type: Application
    Filed: December 8, 2020
    Publication date: March 25, 2021
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 10929137
    Abstract: An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order.
    Type: Grant
    Filed: October 9, 2019
    Date of Patent: February 23, 2021
    Assignee: FUJITSU LIMITED
    Inventors: Hisanari Fujita, Ryohei Okazaki, Takashi Suzuki
  • Patent number: 10824431
    Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.
    Type: Grant
    Filed: May 20, 2019
    Date of Patent: November 3, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Atushi Fusejima, Norihito Gomyo, Ryohei Okazaki
  • Publication number: 20200167226
    Abstract: A processing device performs a first process in a plurality of cycles to update a plurality of resources included in programmable resources. The processing device includes an instruction execution circuit that records that the first process is being executed, and makes an error notification when an error is detected during execution of an instruction, and a retry control circuit that records a type of the first process at a starting point of the first process, judges from the recorded type whether the first process is re-executable upon receiving the error notification during the first process, and instructs re-execution of the first process from a start of the first process in a case where the first process is judged to be re-executable. The instruction execution circuit performs a retry process to re-execute the first process when instructed from the retry control circuit to re-execute the first process.
    Type: Application
    Filed: November 12, 2019
    Publication date: May 28, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Norihito Gomyo, Ryohei Okazaki, YASUNOBU AKIZUKI
  • Publication number: 20200150965
    Abstract: A processing device includes an instruction extractor that extracts target instructions intended for a loop process that is repeatedly performed, from instructions decoded by an instruction decoder, and a loop buffer including entries where each of the target instructions extracted by an instruction extractor are stored. An instruction processor stores a target instruction into one of the entries of the loop buffer, and combines target instructions into one target instruction in a case where resources of an instruction execution circuit used by the target instructions do not overlap, to store the one instruction in one of the entries of the loop buffer, and a selector selects the instruction output from the instruction decoder or the target instruction output from the loop buffer, and outputs the selected instruction to the instruction execution circuit.
    Type: Application
    Filed: October 28, 2019
    Publication date: May 14, 2020
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 10628154
    Abstract: An arithmetic processing device includes a plurality of arithmetic processing units each including, an internal circuit that, in an instruction processing state in which an instruction is processed, processes the instruction and that, in an instruction processing stopped state in which instruction processing is stopped, transitions to a state of power save operation, and a power control circuit that disables the power save operation; and a monitoring circuit that monitors the instruction processing stopped state of the plurality of arithmetic processing units and counts the number of the arithmetic processing units in the instruction processing stopped state. The power control circuit of each of the plurality of arithmetic processing units disables the power save operation of the arithmetic processing unit in the instruction processing stopped state, in a case where the number of the arithmetic processing units in the instruction processing stopped state exceeds a threshold.
    Type: Grant
    Filed: March 21, 2016
    Date of Patent: April 21, 2020
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Norihito Gomyo
  • Publication number: 20200117461
    Abstract: An arithmetic processing device includes: a pipeline circuit including an instruction fetch circuit, an instruction decoder that performs a first branch misprediction determination for a branch instruction, and issues the instructions in-order, a branch instruction processing circuit which performs a second branch misprediction determination for the branch instruction; and a commit processing circuit that executes a commit processing of the processed instructions in-order.
    Type: Application
    Filed: October 9, 2019
    Publication date: April 16, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Hisanari Fujita, Ryohei Okazaki, Takashi Suzuki
  • Publication number: 20200097286
    Abstract: An arithmetic processing device includes: a decoding circuit configured to decode a command; a command execution circuit configured to execute the command decoded by the decoding circuit; a register circuit configured to include a plurality of registers for holding data used by the command execution circuit; an identification information holding circuit configured to store identification information for identifying a register for writing a specific value when the command is a register writing command; a setting circuit configured to hold the specific value; and an operation control circuit configured to execute inhibiting processing when the command is a register reading command, the inhibiting processing including inhibiting an access of the register by the register reading command and selecting the specific value held in the setting circuit.
    Type: Application
    Filed: August 22, 2019
    Publication date: March 26, 2020
    Applicant: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Sota Sakashita, Atushi Fusejima
  • Publication number: 20190384608
    Abstract: An arithmetic circuit performs a floating-point operation. A floating-point register includes entries each allocated to an architectural register or a renaming register. An operation execution controller circuit issues a floating-point operation instruction and outputs a termination report of the floating-point operation before the floating-point operation is terminated. When exception handling is not performed at the time of instruction completion even when an exception is detected in the operation of the floating-point operation instruction, an instruction completion controller circuit outputs a release instruction that indicates a release of a renaming register when instruction execution is completed after the termination report is received.
    Type: Application
    Filed: May 20, 2019
    Publication date: December 19, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Yasunobu Akizuki, Atushi Fusejima, Norihito Gomyo, Ryohei Okazaki
  • Publication number: 20190354368
    Abstract: An arithmetic processing apparatus includes a processor.
    Type: Application
    Filed: April 8, 2019
    Publication date: November 21, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Publication number: 20190347102
    Abstract: An arithmetic processing apparatus includes a processor.
    Type: Application
    Filed: April 24, 2019
    Publication date: November 14, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Publication number: 20190317762
    Abstract: An arithmetic processing unit includes an instruction decoder, first to fourth reservation stations, first and second computing units, first and second load-store units, and an allocation unit. The allocation unit, when the execution instruction is a first instruction that is executable in first and second computing units but not executable in first and second load-store units, allocates the first instruction to first or second reservation station based on a first allocation table, and when the execution instruction is a second instruction that is executable in the first and second load-store units but not executable in the first and second computing units, allocates the second instruction to third or fourth reservation station based on a second allocation table.
    Type: Application
    Filed: March 22, 2019
    Publication date: October 17, 2019
    Applicant: FUJITSU LIMITED
    Inventor: Ryohei Okazaki
  • Patent number: 10430196
    Abstract: An arithmetic processing device includes: a branch prediction unit configured to predict a branch destination address and loop processing based on an address generated by an address generation unit; an instruction buffer unit configured to store an instruction of the address generated by the address generation unit; an instruction decoding unit configured to decode the instruction stored in the instruction buffer unit; and a loop buffer unit configured to store decoding results or decoding intermediate results of instructions of the predicted loop processing that are decoded by the instruction decoding unit and output the stored decoding results or decoding intermediate results a predetermined number of times in response to the loop processing, in which during a period when selecting the output of the loop buffer unit, operations of the address generation unit, the branch prediction unit, the instruction buffer unit, and the instruction decoding unit are stopped.
    Type: Grant
    Filed: May 22, 2017
    Date of Patent: October 1, 2019
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Norihito Gomyo, Yasunobu Akizuki, Takashi Suzuki
  • Publication number: 20190294435
    Abstract: An arithmetic processing unit includes an instruction decoder which decodes a fetch instruction to issue an execution instruction; a reservation station which temporarily stores the execution instruction; and an arithmetic unit which executes the execution instruction, and the fetch instruction includes a multi-flow instruction which is divided into divided instructions and a single instruction. The instruction decoder includes: a pre-decoder including N number of slots each of which divides the multi-flow instruction into divided instructions; a main decoder including N number of slots each of which decodes the instructions to issue an execution instruction; and a pre-decoder buffer including N?K number of slots each of which temporarily stores instructions in the pre-decoder. The instruction decoder repeats transferring the divided instructions and the single instructions from the slots of the pre-decoder and the slots of the pre-decoder buffer to the main decoder as much as possible in order.
    Type: Application
    Filed: February 4, 2019
    Publication date: September 26, 2019
    Applicant: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, YASUNOBU AKIZUKI
  • Patent number: 10048969
    Abstract: A processor includes: an instruction execution unit that executes an instruction; and a branch prediction unit that stores history information indicating every instruction fetches performed a certain number of times before an instruction fetch of a branch prediction target instruction whether the instruction predicted as branch-taken is included and weight tables including weights corresponding to instructions and predicts the branch prediction target instruction to be taken or not-taken. The branch prediction unit, before the instruction fetch of the branch prediction target instruction, obtains the history information and the weights related to the instruction fetches performed the certain number of times to perform a product-sum operation, and at the time of the instruction fetch of the branch prediction target instruction, performs an operation of a result of the product-sum operation and a weight of the branch prediction target instruction to perform branch prediction.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 14, 2018
    Assignee: FUJITSU LIMITED
    Inventors: Ryohei Okazaki, Takashi Suzuki