Abstract: An ATM bus 11 is a bus for performing data transfers in an asynchronous transfer mode, while a control bus 8 is a bus for transferring control signals sent out by a central control section 1 in order to control bus users 10a.about.10d. The bus users 10a.about.10d and a bus arbitration circuit 12 are connected to this ATM bus. The bus users 10A.about.10d are ATM bus users. When the bus users 10a.about.10d simultaneously issue bus use requests, the bus arbitration circuit 12 selects a single bus use request from among these requests. Then, all of the bus users are sent data identifying the bus user which issued the selected bus use request. As a result, only the selected bus user begins a data transfer operation using the ATM bus 11.

Abstract: A multi-stage switching network comprises a plurality of unitary switch matrices each including a number of cross-point circuits each of which in turn includes a memory circuit operatively connected to the associated cross-point switches in a speech path. The plurality of the unitary switch matrices are arranged in a matrix array in which each stage of the multi-stage switching network is constituted by the unitary switch matrices arrayed in at least one column thereof and interconnected through links.