Abstract: A method and an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern by only carrying out a routing process, when a required layout pattern is the same as an existing layout pattern at the transistor-constitution level. Further, a method or an apparatus is provided for forming a layout pattern of a semiconductor integrated circuit comprising automatically reforming a layout pattern without analyzing the logical information down to the transistor-constitution level, when a required layout pattern is not the same as an existing layout pattern in the transistor-constitution level. Therefore, processing can be simplified and operation speed can be increased.

Abstract: A method of forming a semiconductor integrated circuit using a master slice approach includes the steps of: forming a plurality of transistor regions with units of a predetermined number in array on a semiconductor chip; forming a plurality of first wirings extending in parallel at a space therebetween with units of a predetermined length in a discontinuous form so that the first wirings pass through regions corresponding to the transistor regions; forming first contact holes at predetermined positions so that gate regions and source/drain regions of the transistor regions are connected to the first wirings; forming a plurality of second wirings having same forms as the plurality of first wirings so that the second wirings constitute a mesh-like arrangement in combination with the first wirings; and forming second contact holes using a pattern mask programmable in accordance with demanded conditions of a given circuit so that the second contact holes connect the second wirings to the first wirings.