Patents by Inventor Ryoji Matsushima

Ryoji Matsushima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7763964
    Abstract: A semiconductor device includes a circuit board which has a first main surface having first connection pads, a second main surface having second connection pads, a first opening passing through a vicinity of the first connection pads, and a second opening passing through a vicinity of the second connection pads. A first semiconductor element is mounted in a face-down state on the first main surface of the circuit board. First electrode pads are exposed into the second opening and connected to the second connection pads through the second opening. A second semiconductor element is mounted in a face-up state on the second main surface of the circuit board. Second electrode pads are exposed into the first opening and connected to the first connection pads through the first opening.
    Type: Grant
    Filed: February 15, 2008
    Date of Patent: July 27, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Matsushima
  • Patent number: 7755175
    Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.
    Type: Grant
    Filed: November 2, 2006
    Date of Patent: July 13, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Katsuhiro Ishida, Ryoji Matsushima
  • Patent number: 7598604
    Abstract: A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of the first and second semiconductor elements are connected to the first and second connection terminals via bonding wires. A metal circuit board including the first and second connection terminals, and the first and second semiconductor elements are sealed by a sealing material such that parts of the respective connection terminals expose.
    Type: Grant
    Filed: October 19, 2006
    Date of Patent: October 6, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Ryoji Matsushima
  • Patent number: 7569921
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Grant
    Filed: April 6, 2006
    Date of Patent: August 4, 2009
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi
  • Publication number: 20090045525
    Abstract: A semiconductor element is provided with electrode pads which are arranged on a front surface of an element main body, an insulating protection film which covers the front surface of the element main body excepting its outer peripheral area while exposing the electrode pads, and an insulating adhesive layer which is formed to cover a back surface, a sidewall surface and a corner between the front surface and the sidewall surface of the element main body. A plurality of semiconductor elements are stacked on a circuit substrate. The semiconductor elements are adhered via the insulating adhesive layer.
    Type: Application
    Filed: August 14, 2008
    Publication date: February 19, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Ryoji MATSUSHIMA, Naohisa OKUMURA
  • Publication number: 20090032972
    Abstract: A stacked-type semiconductor device includes a plurality of semiconductor elements stacked on a wiring board. Electrode pads of these semiconductor elements are electrically connected to connection pads of the wiring board via metal wires respectively. The long-looped metal wires connected to the upper semiconductor element are fixed by a wire fixing resin portion to the short-looped metal wires connected to the lower semiconductor element. The wire fixing resin portion is filled at least between the metal wires. The stacked semiconductor elements are sealed by a sealing resin layer together with the metal wires.
    Type: Application
    Filed: March 28, 2008
    Publication date: February 5, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Tadanobu OKUBO, Masashi Noda, Ryoji Matsushima
  • Publication number: 20090014894
    Abstract: A stacked semiconductor device includes a first semiconductor element mounted on a wiring board and a second semiconductor element stacked on the first semiconductor element. Electrode pads of the first and second semiconductor elements are electrically connected to connection pads of the wiring board via first and second metal wires. The second metal wire is wired so that a part thereof is in contact with an insulating protective film covering a surface of the first semiconductor element.
    Type: Application
    Filed: July 9, 2008
    Publication date: January 15, 2009
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhiro Ishida, Ryoji Matsushima
  • Publication number: 20070102801
    Abstract: A stack-type semiconductor device according to the present invention includes a circuit board with bonding pads; a first semiconductor chip which includes first electrode pads and is mounted on the circuit board; a second semiconductor chip which includes second electrode pads and is mounted on the first semiconductor chip; a plurality of bonding wires sequentially connecting the bonding pads, the first electrodes and the second electrodes as a whole; and a sealing resin for sealing the first semiconductor chip, the second semiconductor chip and the bonding wires.
    Type: Application
    Filed: November 2, 2006
    Publication date: May 10, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Katsuhiro Ishida, Ryoji Matsushima
  • Publication number: 20070102762
    Abstract: A first semiconductor element and a second semiconductor element each have an electrode forming surface with an electrode pad thereon. The first semiconductor element and the second semiconductor element are stacked to expose each electrode pad and bonded while facing the electrode forming surfaces each other. The electrode pads of the first and second semiconductor elements are connected to the first and second connection terminals via bonding wires. A metal circuit board including the first and second connection terminals, and the first and second semiconductor elements are sealed by a sealing material such that parts of the respective connection terminals expose.
    Type: Application
    Filed: October 19, 2006
    Publication date: May 10, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Ryoji Matsushima
  • Publication number: 20070023922
    Abstract: A semiconductor package includes a circuit board having connection pads formed on a front and back surfaces, and a wiring network connected to these connection pads, as a package base. Metal bumps connected to at least part of the connection pads on the front and back surfaces via the wiring network are formed on the back surface of the circuit board as external connection terminals. One or a plurality of semiconductor elements electrically connected to the connection pad on the front surface side is or are mounted on a first element mounting part provided on the front surface side of the circuit board. One or plurality of semiconductor elements electrically connected to the connection pad on the back surface side is or are mounted on a second element mounting part provided on the back surface side of the circuit board.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi
  • Publication number: 20070023875
    Abstract: A semiconductor package includes a lead frame having an element mounting part and a lead part. A first semiconductor element and a second semiconductor element are sequentially stacked on a principal surface at least on one side of the element mounting part. An insulating resin layer serving as a second adhesive layer is filled between the first semiconductor element and the second semiconductor element. An element-side end portion of a first bonding wire connected to the first semiconductor element is buried in the insulating resin layer.
    Type: Application
    Filed: July 21, 2006
    Publication date: February 1, 2007
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Oonishi, Atsushi Yoshimura
  • Publication number: 20060232288
    Abstract: A semiconductor device has a plurality of bare chips stacked on at least one of first and second main surfaces oppositely arranged on a support substrate, spacers arranged between two bare chips arranged adjacently in up and down direction among the plurality of bare chips, and inner leads which are arranged at both sides in a horizontal direction of the support substrate and are connected to pads of the bare chips via bonding wires, wherein the bonding wires which connect the pads of the bare chips at one end side of the spacers to the corresponding inner leads, are arranged not to contact the bare chip at the other end side of the same spacer.
    Type: Application
    Filed: April 6, 2006
    Publication date: October 19, 2006
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Noboru Okane, Ryoji Matsushima, Kazuhiro Yamamori, Junya Sagara, Yoshio Iizuka, Kuniyuki Ohnishi