Abstract: A filler plug is configured such that: a head portion is formed on an upper end of an external thread; a sealing portion formed at the head portion strongly contacts a funnel-shaped inclined inner peripheral surface formed at one end of an internal thread of a hydraulic device oil passage by tightening the external thread with respect to the internal thread; an upper peripheral surface of the sealing portion is tapered; a circular constricted portion is formed between the sealing portion and the upper end of the external thread; and a dimensionless value of a head portion height H1 from an upper surface of the head portion to the sealing portion, that is, a dimensionless value obtained by dividing the head portion height H1 by a nominal designation value of the external thread portion, ranges from 0.4 to 0.7.

Abstract: According to one embodiment, parallel processing optimization method for an apparatus configured to assign dynamically a part of some of basic modules, into which a program is divided and which comprise a execution rule which defines a executing order of the basic modules and are executable asynchronously with another modules, to threads includes identifiers based on the execution rule wherein the some of the basic modules are assignable to the threads, and configured to execute in parallel the threads by execution modules, the method includes managing the part of some of the basic modules and the identifiers of the threads assigned the part of some of the basic modules, managing an executable set includes the some of the basic modules, calculating transfer costs of the some of the basic modules when data, and selecting one of the basic module with a minimum transfer cost in the transfer costs.

Abstract: An information processing apparatus includes a plurality of execution units and a scheduler which controls assignment of a plurality of basic modules of a program to the plurality of execution units. The scheduler detects a parallel degree representing a parallelization ratio in parallel processing of a program by the plurality of execution units, and detects a load associated with control of assigning the plurality of basic modules in the parallel processing of the program by the plurality of execution units. And then, the scheduler combines two or more basic modules which are successively executed according to a paralleled execution description in order to assign two or more basic modules as a module to a single execution unit, when a value of the parallel degree exceeds a predetermined value and a value of the load exceeds a predetermined value.

Abstract: According to one embodiment, an information processor includes a plurality of execution units, a storage, a generator, and a controller. The storage stores a plurality of basic modules executable asynchronously with another module and a parallel execution control description that defines an execution rule for the basic modules. The generator generates a task graph in which nodes indicating a plurality of tasks relating to the execution of the basic modules are connected by an edge according to the execution order of the tasks, and the nodes and a node of another module in a data dependency relationship are connected by the edge. The controller controls the assignment of the basic modules to the execution units based on the execution rule. The execution units each function as the generator for a basic module to be processed according to the assignment and executes the basic module according to the task graph.

Abstract: According to one embodiment, a grouping method for process units, each including basic modules and data, the process units being assigned to processors in a program for a multiprocessor system, the program including the basic modules and a parallel statement describing relationships between parallel processes for the basic modules, the method includes displaying a dataflow graph visually showing a process status of each process unit based on the parallel statement, and specifying a candidate for a connection of process units on the dataflow graph, wherein the dataflow graph displays data entries, nodes in the basic modules, and edges connecting the data entries and the nodes.

Abstract: According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of first search and second search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node.

Abstract: A debugger includes: a plurality of processor cores; and a scheduler configured to control an allocation of a plurality of basic modules to the processor cores based on an execution rule for enabling parallel execution of a program that is divided into the basic modules that are executable asynchronously with one another, the program being defined with the execution rule of the basic modules for executing the basic modules in time series, wherein the scheduler includes a break point setting module configured to set a group of break points that are designated through a graphical user interface.

Abstract: According to one embodiment, parallel processing optimization method for an apparatus configured to assign dynamically a part of some of basic modules, into which a program is divided and which comprise a execution rule which defines a executing order of the basic modules and are executable asynchronously with another modules, to threads includes identifiers based on the execution rule wherein the some of the basic modules are assignable to the threads, and configured to execute in parallel the threads by execution modules, the method includes managing the part of some of the basic modules and the identifiers of the threads assigned the part of some of the basic modules, managing an executable set includes the some of the basic modules, calculating transfer costs of the some of the basic modules when data, and selecting one of the basic module with a minimum transfer cost in the transfer costs.

Abstract: According to one embodiment, a grouping method for process units, each including basic modules and data, the process units being assigned to processors in a program for a multiprocessor system, the program including the basic modules and a parallel statement describing relationships between parallel processes for the basic modules, the method includes displaying a dataflow graph visually showing a process status of each process unit based on the parallel statement, and specifying a candidate for a connection of process units on the dataflow graph, wherein the dataflow graph displays data entries, nodes in the basic modules, and edges connecting the data entries and the nodes.

Abstract: According to one embodiment, an information processing apparatus comprises a storage storing program modules and parallel execution control description describing relationships of the program modules, a conversion module extracting a part relating to the program module from the parallel execution control description, and creating graph data structure creation information including preceding and succeeding information of the program module, an adding module extracting graph data structure creation information to which the input data is given, creating a node, and adding the created node to a formerly created graph data structure, and an execution module subjecting the graph data structure to at least one of depth-first search and breadth-first search with a restricted breadth, selecting one node from nodes stored in the node memory, and executing a program module corresponding to the selected node.

Abstract: According to one embodiment, an information processing apparatus includes a plurality of execution modules, a system memory shared by the plurality or execution modules, and a scheduler which controls assignment of a plurality of basic modules to the plurality of execution modules in order to execute a program in parallel by the plurality of execution modules. The scheduler saves data items, which is to be input by the execution modules as input data items of the basic modules and is stored in the storage areas of the system memory, in other storage areas of the system memory before the basic modules are executed, and compares the data items stored in the storage areas of the system memory and accessed by the execution modules with the data items saved in the other storage areas of the system memory after the basic modules have been executed.

Abstract: According to one embodiment, an information processing apparatus includes a plurality of execution units and a scheduler which controls assignment of a plurality of basic modules of a program to the plurality of execution units. The scheduler detects a parallel degree representing a parallelization ratio in parallel processing of a program by the plurality of execution units, and detects a load associated with control of assigning the plurality of basic modules in the parallel processing of the program by the plurality of execution units. And then, the scheduler combines two or more basic modules which are successively executed according to a paralleled execution description in order to assign two or more basic modules as a module to a single execution unit, when a value of the parallel degree exceeds a predetermined value and a value of the load exceeds a predetermined value.

Abstract: According to one embodiment, an encoding circuit includes a taking-over unit which takes over probability tables of divided regions of a previous frame image of a frame image having divided regions to divided regions of a present frame image, respectively, an acquiring unit which acquires a parameter of an adjacent macro block of the previous frame image when the macro block is located on a boundary between the divided regions, a selecting unit which calculates the parameter of the macro block to select one of probability models in the probability table, and an encoding unit which arithmetically encodes a residual signal in the frame image on the basis of the selected probability model to generate an encoded bit string.

Abstract: According to one embodiment, a program processing method includes converting parallel execution control description into graph data structure generating information, extracting a program module based on preceding information included in the graph data structure generating information when input data is given, generating a node indicating an execution unit of the program module for the extracted program module, adding the generated node to a graph data structure configured based on preceding and subsequent information defined in the graph data structure generating information, executing a program module corresponding to a node included in a graph data structure existing at that time, by setting values for the parameter, based on performance information of the node when all nodes indicating a program module defined in the preceding information have been processed, and obtaining and saving performance information of the node when a program module corresponding to the node has been executed.

Abstract: According to one embodiment, an encoding circuit includes a taking-over unit which takes over probability tables of divided regions of a previous frame image of a frame image having divided regions to divided regions of a present frame image, respectively, an acquiring unit which acquires a parameter of an adjacent macro block of the previous frame image when the macro block is located on a boundary between the divided regions, a selecting unit which calculates the parameter of the macro block to select one of probability models in the probability table, and an encoding unit which arithmetically encodes a residual signal in the frame image on the basis of the selected probability model to generate an encoded bit string.

Abstract: According to one embodiment, a recording medium which records a compiler program which is loaded on a memory of a computer and executed to have the following functions analyzing a source program to detect a branched part in control of the program, and dividing the source program into divided programs which are program pieces executed without the branched part and parts executed while being branched.

Abstract: A processor system includes a plurality of first processors, a second processor, and a memory device. The first processors execute image processing on first image data to generate second image data. Each of the first processors processes the first image data in pixel group units. The memory device holds luminance components of at least one of the first image data and the second image data, in a first memory space with consecutive addresses. The memory device also holds the luminance components contained in the same pixel group, in the first memory space at the consecutive addresses.

Abstract: According to one embodiment, when a plurality of video frames are encoded in parallel, a rate control is executed on the basis of the generated bit amount in the encoded video frames, and encoding the video frames and a rate control at a synchronization point 6-2 are executed in parallel.

Abstract: An image compression apparatus of this invention has an input unit configured to input image data of a moving picture, a first encoding processor configured to apply compression-encoding processing to the image data input from the input unit using a plurality of compression-encoding modes, a remaining battery level management unit configured to manage the remaining battery level of hardware on which the image compression apparatus is mounted, and a first controller configured to limit some of the plurality of compression-encoding modes which are configured to be processed by the first encoding processor when the remaining battery level managed by the remaining battery level management unit becomes lower than a predetermined setting value.

Abstract: An information processing device includes a first unit which extracts intra prediction information included in a bit stream of video codec, and a second unit which converts the resolution of image data into an image whose resolution is higher than that of an original image, wherein the second unit converts the pixels into high resolution images by performing interpolation processing for pixels of the image data on the basis of the intra prediction information.