Abstract: To apply an on-board electronic controller having a relay control driver circuit for performing ON/OFF control of a relay that connects and shuts off a wire from a battery. The on-board electronic controller includes: a switch circuit that is connected to an output unit of the relay control driver circuit to draw out a current; and a control circuit that activates the switch circuit when an abnormality occurs in the vehicle, to cause the switch circuit to draw out the current from the output unit so as not to turn on the relay. This prevents sticking of the relay to ON even in a case where an output harness of a relay control driver is short-circuited to another signal harness or a power supply and GND line.

Abstract: A power supply apparatus that can realize ripple reduction, and an electronic control unit including the power supply apparatus are provided. In view of this, a PWM controller generates a PWM signal, and a PFM controller generates a PFM signal having a phase independent of the PWM signal. A level-fixed period generating circuit sets a level-fixed period having a start timing at a selection timing set to an edge of the PFM signal. A mode selecting circuit selects, at the selection timing and as a switching control signal, the PWM signal instead of the PFM signal, and controls a logic level of the switching control signal in the level-fixed period starting at the selection timing, such that the logic level becomes a fixed logic level.

Abstract: A power supply apparatus that can realize ripple reduction, and an electronic control unit including the power supply apparatus are provided. In view of this, a PWM controller generates a PWM signal, and a PFM controller generates a PFM signal having a phase independent of the PWM signal. A level-fixed period generating circuit sets a level-fixed period having a start timing at a selection timing set to an edge of the PFM signal. A mode selecting circuit selects, at the selection timing and as a switching control signal, the PWM signal instead of the PFM signal, and controls a logic level of the switching control signal in the level-fixed period starting at the selection timing, such that the logic level becomes a fixed logic level.

Abstract: A load drive system for driving a load supplied with power from a power line includes a control unit which controls switching between the power line and the load and a communication unit which communicates using voltage and current of the power line. When performing the switching, the control unit controls, based on a width of a transition period of the power-line current, the transition period being attributable to the switching, timing of the switching so as to move the transition period away from a center of a period corresponding to a symbol communicated by the communication unit.

Abstract: A load drive system for driving a load supplied with power from a power line includes a control unit which controls switching between the power line and the load and a communication unit which communicates using voltage and current of the power line. When performing the switching, the control unit controls, based on a width of a transition period of the power-line current, the transition period being attributable to the switching, timing of the switching so as to move the transition period away from a center of a period corresponding to a symbol communicated by the communication unit.

Abstract: A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.

Abstract: A temperature dependence adjustable operational amplifier circuit which suppresses a change in a gain caused by a change in an input voltage is provided. In an operational amplifier including a first input terminal and an output terminal, an operational amplifier having an inverting input terminal and a non-inverting input terminal, an input resistance circuit, and a feedback resistance circuit, each of the input and feedback resistor circuits has a resistor and a trimming resistor, which are different in temperature coefficient from each other, connected in series with each other, and a source-drain path of a MOS transistor included in the trimming resistor circuit is disposed between resistance and an inverting input terminal, and a substrate potential thereof is set to a potential of the inverting input terminal of the operational amplifier.

Abstract: An amplifier circuit is configured to be preceded by a single-ended-to-differential translate circuit using a BTL configuration operating at a low voltage and succeeded by amplifiers to amplify output signals VOT and VOB from the single-ended-to-differential translate circuit. The amplifier circuit activates a mute function of the subsequent amplifiers during state transition when the single-ended-to-differential translate circuit turns on. Consequently, the amplifier circuit fixes output signals OUTP and OUTN to 0 V and masks an output noise. The amplifier circuit inactivates the mute function after signals VOT and VOB become stable. Thereby, the amplifier circuit is capable of easily preventing a pop noise using a BTL configuration requested for high voltage output to drive a piezoelectric actuator.

Abstract: Disclosed is a piezoelectric actuator drive unit that includes a piezoelectric actuator drive amplifier and a piezoelectric actuator drive unit power supply. Combinations of high and low signal levels of a first control signal, which controls the supply voltage and amplifier bias voltage of the piezoelectric actuator drive amplifier, and a second control signal, which controls the driving force of the piezoelectric actuator drive amplifier, are associated with a haptic feedback function, a receiver function for generating an audio output, and a speaker function for generating music or the like. Thus, the piezoelectric actuator drive unit, which vibrates a piezoelectric actuator, is adapted to the haptic feedback function, the receiver function, and the speaker function, and can optimize its power and drive amplifier characteristics.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions.

Abstract: A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal. A first signal and a second signal supplied from outside through a first signal path and a second signal path are respectively transferred to the pulse generator. When a rising time up to the full amplitude at any one of buffers in the first signal path and the second signal path is longer than a pulse width of a pulse to be formed by the pulse generator, the difference in phase between the first signal and the second signal is caused to correspond to a pulse width of a first pulse.

Abstract: The present invention provides a semiconductor integrated circuit device equipped with at least one pulse generator which generates a pulse of a pulse with shorter than a rising time up to the full amplitude of a transfer signal.