Abstract: An optical transceiver includes an optical transmitter, an optical receiver, a first processing unit for controlling a section of the optical transmission circuit, a second processing unit for controlling a section of the optical reception circuit, and a signal line. First and second memory regions constitute a MDIO register space. The selection signal is set to a first level when the first memory region includes a MDIO register, and alternatively is set to a second level when the second memory region includes the MDIO register. The first processing unit responds to another MDIO frame having an OP code set to other than “00h” when the selection signal is at the first level, and the second processing unit alternatively responds to the another MDIO frame when the selection signal is at the second level.

Abstract: An optical transceiver includes an optical transmitter, an optical receiver, a first processing unit for controlling a first section of the optical transmission circuit and the optical reception circuit, a second processing unit for controlling a second section of the optical transmission circuit and the optical reception circuit, and a signal line. A first and second memory regions constitute a MDIO register space, the selection signal is set to a first level when the first memory region includes a MDIO register, and alternatively set to a second level when the second memory region includes the MDIO register, and the first processing unit responds to another MDIO frame having an OP code set to other than “00h” when the selection signal is at the first level, and the second processing unit alternatively responds to the another MDIO frame when the selection signal is at the second level.

Abstract: An optical transceiver that shortens an elapsed time for loading data from an external device, and a method of loading data are disclosed. The optical transceiver includes an inner memory, a central processing unit (CPU), and a serial communication line connecting the CPU with the external device. The CPU actively loads data stored in the external device into the inner memory through the serial communication line by operating as a master device in the serial communication line.

Abstract: An optical transceiver that shortens an elapsed time for loading data from an external device, and a method of loading data are disclosed. The optical transceiver includes an inner memory, a central processing unit (CPU), and a serial communication line connecting the CPU with the external device. The CPU actively loads data stored in the external device into the inner memory through the serial communication line by operating as a master device in the serial communication line.

Abstract: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.

Abstract: An apparatus including a plurality of internal devices that communicates concurrently with a controller by one of the MDIO protocol and the SPI protocol is disclosed. The controller of the invention couples with respective devices by the point-to-point arrangement. The controller couples with the external apparatus by the MDIO protocol and receives a packet containing an address of one of internal devices, the controller communicates with the device defined by the address by the protocol attributed to the device.

Abstract: An electronic apparatus is disclosed, where the apparatus revises the micro-program thereof reliably. The apparatus provides a master and slave CPUs each having a memory. The micro-program to be revised is temporarily set in the memory of the slave CPU. Interrupting the master CPU, and connecting the slave CPU with the master CPU via an auxiliary interface independent of the inner interface (bus), the micro-program to be revised and stored in the memory of the slave CPU is transferred to the memory of the master CPU through the auxiliary interface. Auxiliary interface is cut during the normal operation of the master CPU.

Abstract: An optical transceiver able to communicate with an upper device is disclosed. The optical transceiver distinguishes the peripheral interface from the CPU. The CPU monitors includes MDIO register that stores inner conditions of the optical transceiver. The peripheral interface is coupled with the upper device with the MDIO bus, and the CPU with the parallel bus. The upper device acquires one of the conditions by defining the address of the MDIO register and receiving data through the peripheral interface.

Abstract: An optical receiver is provided as a device capable of detecting a small optical power with satisfactory accuracy and detecting the optical power in a wide dynamic range. In the optical receiver a bias generator applies a variable voltage to an avalanche photodiode (APD). First and second current sensors generate first and second detected signals according to a photocurrent. A controller calculates an optical power, using either one of the detected signals. The first current sensor includes a current mirror circuit and generates a first detected signal by measuring an electric current proportional to the photocurrent. The second current sensor is disposed between the bias generator and the current mirror circuit, and the maximum of the photocurrent detectable by this second current sensor is greater than the maximum of the photocurrent detectable by the first current sensor.

Abstract: An optical receiver is provided as a device capable of detecting a small optical power with satisfactory accuracy and detecting the optical power in a wide dynamic range. In the optical receiver a bias generator applies a variable voltage to an avalanche photodiode (APD). First and second current sensors generate first and second detected signals according to a photocurrent. A controller calculates an optical power, using either one of the detected signals. The first current sensor includes a current mirror circuit and generates a first detected signal by measuring an electric current proportional to the photocurrent. The second current sensor is disposed between the bias generator and the current mirror circuit, and the maximum of the photocurrent detectable by this second current sensor is greater than the maximum of the photocurrent detectable by the first current sensor.