Patents by Inventor Ryutaro Yamanaka

Ryutaro Yamanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8723777
    Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
    Type: Grant
    Filed: July 27, 2012
    Date of Patent: May 13, 2014
    Assignee: Panasonic Corporation
    Inventors: Minoru Okamoto, Ryutaro Yamanaka, Kazuhiro Okabayashi, Yukihiro Sasagawa
  • Publication number: 20120293526
    Abstract: A panel control device includes a programmable array. This programmable array operates in accordance with a configuration code and includes a plurality of first-class elements and at least one second-class element. This provides a panel control device requiring a small circuit area, being suitable for system-on-chip (SoC) mounting, and driving a liquid crystal display device having various specifications also in the future.
    Type: Application
    Filed: July 27, 2012
    Publication date: November 22, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Minoru OKAMOTO, Ryutaro YAMANAKA, Kazuhiro OKABAYASHI, Yukihiro SASAGAWA
  • Patent number: 7634291
    Abstract: A communication terminal apparatus wherein even in a case of occurrence of a compressed mode, an evaluation can be performed by a detecting function to select an appropriate TFC (TRANS Format Combination). In this communication terminal apparatus, upon occurrence of a compressed mode, a compressed mode information generating part (173) outputs both a gap section and a gap start slot number for application to a transmission power determining part (174), which then counts the slots in which the TFC transmission power exceeds an upper limit for each TFC. At this moment, the transmission power determining part (174) replaces the TFC transmission power, for the slots of the gap section, by the TFC transmission power of the slots other than those of the gap section. ATFC status managing part (175) determines, based on the counting result of the transmission power determining part (174), the status of each TFC.
    Type: Grant
    Filed: June 21, 2005
    Date of Patent: December 15, 2009
    Assignee: Panasonic Corporation
    Inventors: Ryutaro Yamanaka, Noriaki Minamida
  • Patent number: 7529559
    Abstract: Digital signal processing section 103 has reconfigurable device 131, and reconfigurable device 131 configures decoding section 133 and coding section 134 by programming data. Decoding section 133 acquires synchronization from a signal output from reception section 121, and demodulates and decodes the signal. CPU 105 downloads programming data of another radio communication system to store in storage section 106 via general bus 104. Further, CPU 105 reads out the stored programming data, and reconfigures reconfigurable device 131. Storage section 106 stores the programming data.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: May 5, 2009
    Assignee: Panasonic Corporation
    Inventors: Ryutaro Yamanaka, Toshihiro Ishikawa
  • Patent number: 7496048
    Abstract: A compressed mode outbound propagation path quality information transmitting method and an outbound propagation path quality information transmitting apparatus are disclosed that enable a mobile station to maintain reception performance virtually equal to that of a conventional compressed mode outbound propagation path quality information transmitting method, and enable operation control relating to received signal measurement and so forth necessary for generating outbound propagation path quality information transmitted on an uplink to be performed easily. Provision is made so that, in compressed mode in which transmission gap intervals appear in both a downlink and uplink, a mobile station does not carry over outbound propagation path quality information generated based on a received signal preceding the beginning of that downlink transmission gap interval until that downlink transmission gap interval and uplink transmission gap interval both end.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: February 24, 2009
    Assignee: Panasonic Corporation
    Inventors: Tetsuya Ikeda, Ryutaro Yamanaka, Hidetoshi Suzuki
  • Publication number: 20080229081
    Abstract: Each cell comprises a first selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; a second selector which accepts K-pieces (K is a natural number of 2 or more) of data, and then outputs a single piece of data; an arithmetic and logic unit which accepts selection output of the first selector and selection output of the second selector in N bits (N is a natural number of 2 or more), and performs a logic operation that is selected from a plurality of logic operations on accepted data of N bits; a selection controller which supplies, to the first selector and the second selector, a data selection control signal for indicating data to be selected; and an ALU controller which supplies, to the arithmetic and logic unit, an ALU control signal that designates the logic operation to be executed.
    Type: Application
    Filed: March 12, 2008
    Publication date: September 18, 2008
    Inventor: Ryutaro Yamanaka
  • Publication number: 20080220802
    Abstract: A communication terminal apparatus wherein even in a case of occurrence of a compressed mode, an evaluation can be performed by a detecting function to select an appropriate TFC (TRANS Format Combination). In this communication terminal apparatus, upon occurrence of a compressed mode, a compressed mode information generating part (173) outputs both a gap section and a gap start slot number for application to a transmission power determining part (174), which then counts the slots in which the TFC transmission power exceeds an upper limit for each TFC. At this moment, the transmission power determining part (174) replaces the TFC transmission power, for the slots of the gap section, by the TFC transmission power of the slots other than those of the gap section. ATFC status managing part (175) determines, based on the counting result of the transmission power determining part (174), the status of each TFC.
    Type: Application
    Filed: June 21, 2005
    Publication date: September 11, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryutaro Yamanaka, Noriaki Minamida
  • Publication number: 20080072129
    Abstract: A digital signal processor includes an instruction executer configured to execute instructions. The instruction executer determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The instruction executer outputs a processed data including the first minimum data and the second minimum data. A bit length of the first minimum data is equal to n bits in length. A bit length of the second minimum data is equal to n bits in length. A bit length of the processed data is equal to at least 2n bits in length.
    Type: Application
    Filed: October 30, 2007
    Publication date: March 20, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryutaro YAMANAKA, Hidetoshi SUZUKI, Hideyuki KABUO, Minoru OKAMOTO, Kevin STONE
  • Patent number: 7325184
    Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2 n bits in length.
    Type: Grant
    Filed: December 28, 2004
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Mark Stone
  • Publication number: 20070067379
    Abstract: A reconfigurable data processing apparatus. In this apparatus, many cells A 100 for performing ALU processing and cells B 150 for performing bit processing are arranged, each cell includes n-bit input/output ports and the cells are connected through a network with n-bit buses. Furthermore, when the number of output bits is smaller than n, cell B 150 fixes bits of orders irrelevant to outputs to “0” or “1.” When the bussed ALU processing part and bit processing part are combined to perform data processing, this makes it possible to execute ALU processing and bit processing efficiently and realize high-speed, parallel processing.
    Type: Application
    Filed: October 6, 2004
    Publication date: March 22, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRAIL CO., LTD.
    Inventors: Hiroyuki Motozuka, Ryutaro Yamanaka
  • Publication number: 20070055651
    Abstract: A search support apparatus that makes it easy to search for an object and communicate with a communication apparatus which manages the object. In this apparatus, when control section 105 receives object information from demodulation section 102a, it reads object information (search conditions) registered in object information section 103b in condition registration section 103, compares the information with the input object information, generates a control signal for controlling a reporting operation of operation section 106 according to the comparison result and outputs the control signal to operation section 106. Operation section 106 executes a reporting operation according to the comparison result of the object information at control section 105, and is constructed of rotation control section 106a and vibration motor 106b as shown in FIG. 4. Rotation control section 106a controls the intensity or the period of vibration of vibration motor 106b according to the control signal input from control section 105.
    Type: Application
    Filed: September 29, 2004
    Publication date: March 8, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryutaro Yamanaka, Takao Nihei
  • Publication number: 20070033153
    Abstract: A disaster prediction system that provides a plurality of mobile communications apparatuses with a function for detecting abnormal signals that are effective in natural disaster prediction, manages location information for the mobile communications apparatuses and appropriately sets areas of natural disaster prediction, collects a plurality of abnormality detection signals from the mobile communications apparatuses, analyzes these signals per area of prediction, improves the accuracy of natural disaster occurrence prediction, and transmits natural disaster-related information to a plurality of mobile communications apparatuses present in the areas of prediction.
    Type: Application
    Filed: October 25, 2004
    Publication date: February 8, 2007
    Inventors: Ryutaro Yamanaka, Hiroyuki Motozuka, Mitsuru Uesugi
  • Patent number: 7139968
    Abstract: A digital signal processor configured to perform a Viterbi algorithm includes an instruction fetching unit that fetches instructions and a decoding unit that decodes the instructions fetched by the instruction fetching unit. The digital signal processor also includes an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register—register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data, and the execution unit outputs new path metrics. Each of the first data, the second data, the third data, and the fourth data is one of four results obtained by adding one of two path metrics to one of two branch metrics.
    Type: Grant
    Filed: December 31, 2003
    Date of Patent: November 21, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Mark Stone
  • Publication number: 20060087980
    Abstract: A compressed mode outbound propagation path quality information transmitting method and an outbound propagation path quality information transmitting apparatus are disclosed that enable a mobile station to maintain reception performance virtually equal to that of a conventional compressed mode outbound propagation path quality information transmitting method, and enable operation control relating to received signal measurement and so forth necessary for generating outbound propagation path quality information transmitted on an uplink to be performed easily. Provision is made so that, in compressed mode in which transmission gap intervals appear in both a downlink and uplink, a mobile station does not carry over outbound propagation path quality information generated based on a received signal preceding the beginning of that downlink transmission gap interval until that downlink transmission gap interval and uplink transmission gap interval both end.
    Type: Application
    Filed: September 27, 2004
    Publication date: April 27, 2006
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ikeda, Ryutaro Yamanaka, Hidetoshi Suzuki
  • Publication number: 20060003795
    Abstract: Digital signal processing section 103 has reconfigurable device 131, and reconfigurable device 131 configures decoding section 133 and coding section 134 by programming data. Decoding section 133 acquires synchronization from a signal output from reception section 121, and demodulates and decodes the signal. CPU 105 downloads programming data of another radio communication system to store in storage section 106 via general bus 104. Further, CPU 105 reads out the stored programming data, and reconfigures reconfigurable device 131. Storage section 106 stores the programming data.
    Type: Application
    Filed: October 6, 2003
    Publication date: January 5, 2006
    Applicant: Matrsushita Electric Industrial Co.,LTD
    Inventors: Ryutaro Yamanaka, Toshihiro Ishikawa
  • Patent number: 6957310
    Abstract: Counter control section 101 increments a row number and column number on a two-dimensional array for a block interleave expressed by a matrix two-dimensional array, outputs the incremented numbers as the read address values, bit inversion apparatus 102 performs bit inversion using the read address values as inputs, column conversion section 103 outputs the address values corresponding to the bit inversion output values and the column numbers from counter control section 101 as the column conversion values, shift register 104 bit-shifts the output values of bit inversion apparatus 102 and outputs as the address offset values, adder 106 adds up the address offset values and column conversion values and size comparison section 106 compares the addition value with the interleave size and outputs data which is not greater than the interleave size as address values.
    Type: Grant
    Filed: October 6, 2000
    Date of Patent: October 18, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tetsuya Ikeda, Ryutaro Yamanaka
  • Publication number: 20050163233
    Abstract: A digital signal processor includes a functional unit configured to execute instructions. The functional unit determines a first minimum data of a first data and a second data, in parallel with a determination of a second minimum data of a third data and a fourth data. The functional unit outputs processed data including the first minimum data and the second minimum data. Each bit length of the first minimum data and the second minimum data is equal to n bits in length. A bit length of the processed data is equal to 2n bits in length.
    Type: Application
    Filed: December 28, 2004
    Publication date: July 28, 2005
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Stone
  • Publication number: 20050163259
    Abstract: A calculation processing apparatus and a calculation processing method intended to suppress the operating speed of an LSI to a low level and realize size reduction, weight reduction and cost reduction of a portable terminal. Addition sections (120a-1 to 4) obtain channel estimation coefficients after updating based on a channel estimation coefficient before updating, multiplication result of a multiplier (110a), GND and a counter value of a 2-bit counter (130) or selection signal (600). The 2-bit counter (130) generates 2-bit numerical values in a predetermined clock number, outputs the respective bits to addition sections (120a-2, 3) and outputs a 2-bit counter value to a storage section (140).
    Type: Application
    Filed: July 9, 2003
    Publication date: July 28, 2005
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventor: Ryutaro Yamanaka
  • Publication number: 20040177313
    Abstract: A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions, a decoding unit that decodes the instructions fetched by the instruction fetching unit; and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes an arithmetic logic unit configured to perform a register-register arithmetic logic operation. The arithmetic logic unit compares a first data with a second data, in parallel with a comparison of a third data with a fourth data. The first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs new path metrics.
    Type: Application
    Filed: December 31, 2003
    Publication date: September 9, 2004
    Applicant: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Mark Stone
  • Patent number: 6735714
    Abstract: A digital signal processor capable of performing a Viterbi algorithm is provided. The digital signal processor includes an instruction fetching unit that fetches instructions; a decoding unit that decodes the instructions fetched by the instruction fetching unit, and an execution unit that executes the instructions decoded by the decoding unit. The execution unit includes a first comparing unit that compares first data with second data and a second comparing unit that compares third data with fourth data. The first comparing unit and the second comparing unit operate in parallel. Also, the first data, the second data, the third data, and the fourth data can each be one of four results obtained by adding one of two path metrics to one of two branch metrics. The execution unit outputs any two new path metrics in a high order position and a low order position respectively.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: May 11, 2004
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryutaro Yamanaka, Hidetoshi Suzuki, Hideyuki Kabuo, Minoru Okamoto, Kevin Stone