Patents by Inventor S Paul Tucker
S Paul Tucker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7315542Abstract: A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.Type: GrantFiled: September 30, 2002Date of Patent: January 1, 2008Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Mercedes E Gil, S. Paul Tucker, Edmundo Rojas
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Patent number: 7313090Abstract: In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.Type: GrantFiled: September 26, 2002Date of Patent: December 25, 2007Assignee: Avago Technologies General IP (Singapore) Pte. Ltd.Inventors: Edmundo Rojas, S. Paul Tucker, Mercedes E Gil
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Patent number: 7209478Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.Type: GrantFiled: May 31, 2002Date of Patent: April 24, 2007Assignee: Palau Acquisition Corporation (Delaware)Inventors: Edmundo Rojas, S. Paul Tucker
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Patent number: 7184411Abstract: An infiniband architecture switch, includes a plurality of ports each configured to receive switch parameters, identify at least one data-packet error condition responsive to the switch parameters, generate a trap-initialization signal when the at least one data-packet error condition matches a trap-error condition, and a switch manager configured to receive the trap-initialization signal. A method for generating a switch manager control signal includes identifying at least one data-packet error condition in an infiniband architecture switch, determining when the at least one data-packet error condition matches a trap-error condition, generating a trap-initialization signal responsive to the trap-error condition, and forwarding the trap-initialization signal to a switch manager.Type: GrantFiled: December 17, 2002Date of Patent: February 27, 2007Assignee: Palau Acquisition Corporation (Delaware)Inventors: S. Paul Tucker, Venitha L Manter
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Patent number: 6919898Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.Type: GrantFiled: January 21, 2000Date of Patent: July 19, 2005Assignee: Hewlett-Packard Development Company, L.P.Inventors: S. Paul Tucker, Kyle R. Berry
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Patent number: 6898752Abstract: A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.Type: GrantFiled: May 31, 2002Date of Patent: May 24, 2005Assignee: Agilent Technologies, Inc.Inventor: S. Paul Tucker
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Publication number: 20040153849Abstract: An infiniband architecture switch, includes an error checker having a plurality of inputs and an output signal bus, the error checker configured to identify at least one data-packet error condition responsive to signals at the plurality of inputs, and an error recorder communicatively coupled to the error checker via the output signal bus wherein the error recorder contains a representation of data-packet errors. A method for identifying data-packet errors includes, monitoring for the occurrence of at least one data-packet error condition in a port of an infiniband architecture switch, encoding a representation of the at least one data-packet error condition, and forwarding the representation to an error recorder.Type: ApplicationFiled: December 17, 2002Publication date: August 5, 2004Inventors: S. Paul Tucker, Venitha L. Manter
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Publication number: 20040114531Abstract: An infiniband architecture switch, includes a plurality of ports each configured to receive switch parameters, identify at least one data-packet error condition responsive to the switch parameters, generate a trap-initialization signal when the at least one data-packet error condition matches a trap-error condition, and a switch manager configured to receive the trap-initialization signal. A method for generating a switch manager control signal includes identifying at least one data-packet error condition in an infiniband architecture switch, determining when the at least one data-packet error condition matches a trap-error condition, generating a trap-initialization signal responsive to the trap-error condition, and forwarding the trap-initialization signal to a switch manager.Type: ApplicationFiled: December 17, 2002Publication date: June 17, 2004Inventors: S. Paul Tucker, Venitha L. Manter
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Publication number: 20040062244Abstract: A method and structure for the handling and discarding of packets in a packet data network. The method includes a packet data network receiving one or more packets from one or more remote locations and initiating a transfer of a packet of the one or more packets to a remote destination. The remote destination is operable to act as a destination port of a switch. The transfer of the packet is initiated while the packet of the one or more packets is being received, and the packet validity is also checked while the transfer of the packet is initiated. If the packet is invalid, the transfer of the packet of the one or more packets to the remote destination is canceled. Determining packet validity includes inspection of a packet header. The structure has a receive link determining packet validity and passing this error signal to a packet processor. The packet processor has a packet transfer request generator, a packet checker, packet reader, packet memory and tag memory.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Mercedes E. Gil, S. Paul Tucker, Edmundo Rojas
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Publication number: 20040062266Abstract: In general, a system and method for providing data packet flow control is disclosed. Generally, a switch is provided that contains a series of ports, an arbiter and a hub. The arbiter determines an outgoing port, wherein the outgoing port is one port for the series of ports, for transmission of a data packet received by the switch, determines whether the outgoing port is available to receive the received data packet, and regulates transmission of the received data packet to a destination end node. The hub provides a point-to-point connection between any two of the series of ports and the arbiter.Type: ApplicationFiled: September 26, 2002Publication date: April 1, 2004Inventors: Edmundo Rojas, S. Paul Tucker, Mercedes E. Gil
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Publication number: 20040030763Abstract: Internal memory elements of vendor-specific network devices are made available using standardized network protocol packets. In accordance with the invention, reserved values of an attribute identifier field may be mapped to implementation-specific nodes within a particular manufacturer's network device, while a set of reserved attribute modifier values may be mapped to implementation-specific memory elements within the node specified by the value of the attribute identifier. Access to implementation-specific device internals is therefore made possible using the standard network protocol.Type: ApplicationFiled: August 8, 2002Publication date: February 12, 2004Inventors: Venitha L. Manter, Norman Chou, Prasad Vajjhala, S. Paul Tucker
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Publication number: 20040001487Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar at 1×, 4×, and 12× speeds. A state machine that controls the changing of the speed of operation of the port.Type: ApplicationFiled: June 28, 2002Publication date: January 1, 2004Inventors: S. Paul Tucker, Edmundo Rojas, Mercedes E. Gil
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Publication number: 20030223416Abstract: A switch for use with an InfiniBand network. The switch includes a crossbar that redirects packet-based data based on a forwarding table. At least one port that receives data from a network and selectively transfers that data to the crossbar using a variable number of virtual lanes. A state machine controls the changing of the number of virtual lanes.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Inventors: Edmundo Rojas, S. Paul Tucker
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Publication number: 20030226085Abstract: A combination error detector to detect errors in an InfiniBand packet. The detector includes registers that stores fields of an InfiniBand packet as the packet is being received and comparison logic that, as the fields are stored in the registers, compares the fields with check values and when an error is detected sets a flag corresponding to the error. After the packet has been completely received and all checks have been complete, all of the error flags are prioritized in accordance with the InfiniBand Architecture Specification.Type: ApplicationFiled: May 31, 2002Publication date: December 4, 2003Inventor: S. Paul Tucker
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Publication number: 20030193894Abstract: An early detection system is presented in which flow control logic is used to continually assess the capacity of a buffer memory. The flow control logic maintains an update of the buffer memory based on the buffer memories ability to store information associated with one of eight virtual lanes. As a result of the assessment, the flow control logic is capable of generating an early full detect signal. The early full detect signal denotes the capability of the buffer memory to hold packet information in a specific virtual lane. Packet checker logic receives the early full detect signal and assesses the first byte (e.g. first three bits) of a packet header, to determine whether the buffer memory can store information. If the packet passes the early detect test a second test is performed to determine if the buffer memory has enough space to store the packet. Should the buffer memory be unable to store information, the packet is discarded.Type: ApplicationFiled: April 12, 2002Publication date: October 16, 2003Inventors: S. Paul Tucker, Edmundo Rojas
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Publication number: 20030058221Abstract: Regions of frame buffer memory are selectively read by a computer graphics system in a bandwidth efficient manor. Attribute data for each pixel is stored in the frame buffer memory array. This attribute data, when decoded, selects which regions of frame buffer memory are required for display of each pixel. Pixels are grouped as tiles. Before each tile is displayed, attribute data is read for that tile, then decoded, and the frame buffer memory is accessed only for those regions that are needed to display the current tile of pixels.Type: ApplicationFiled: January 21, 2000Publication date: March 27, 2003Inventors: S. Paul Tucker, Kyle R. Berry
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Patent number: 6437781Abstract: A computer graphics system includes an apparatus for fog blending colors to be displayed on a graphics display of the computer graphics system. The computer graphics system includes a rendering parameter calculation unit responsive to data of a primitive, that determines a cooked exponent value and a color value for at least one pixel of the primitive. In addition, the system includes a fog unit responsive to the cooked exponent value for each pixel of the primitive, that determines a fog blending factor for each pixel of the primitive, wherein the fog blending factor is one of an exponential fog blending factor and an exponential-squared fog blending factor.Type: GrantFiled: May 30, 1997Date of Patent: August 20, 2002Assignee: Hewlett-Packard CompanyInventors: S. Paul Tucker, Bradly J. Foster, Steven J. Kommrusch
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Patent number: 6219071Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system. In architecture, the system is implemented as follows. The geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.Type: GrantFiled: October 6, 1998Date of Patent: April 17, 2001Assignee: Hewlett-Packard CompanyInventors: Alan S. Krech, Jr., Theodore G. Rossin, Edmundo Rojas, Michael S McGrath, Ted Rakel, Glenn W Strunk, Jon L Ashburn, S Paul Tucker
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Patent number: 6184902Abstract: The invention provides for a system and method for minimizing space requirements and increasing speed in a geometry accelerator for a computer graphics system by providing a branch central intelligence mechanism. Architecturally, the geometry accelerator includes a plurality of processing elements (e.g., an arithmetic logic unit, a multiplier, a divider, a compare mechanism, a clamp mechanism, etc.) and a plurality of control units (e.g., a transform mechanism, a decomposition mechanism, a clip mechanism, a bow-tie mechanism, a light mechanism, a classify mechanism, a plane equation mechanism, a fog mechanism, etc.) that utilize the processing elements for performing data manipulations upon image data. In accordance with the invention, the control units are implemented in a read-only memory (ROM) via microcode. A next address field is associated with each of the microcode instructions and defines a location in the ROM of a next instruction to be executed.Type: GrantFiled: April 30, 1997Date of Patent: February 6, 2001Assignee: Hewlett-Packard CompanyInventors: Alan S. Krech, Jr., Theodore G. Rossin, Glenn W Strunk, Michael S McGrath, Edmundo Rojas, S Paul Tucker, Jon L Ashburn, Ted Rakel
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Patent number: 5956042Abstract: A system and method computes the color of a plurality of vertices of one or more graphic primitives in a graphics accelerator. The method includes the steps of receiving lighting properties of a primitive vertex and determining whether predetermined lighting properties of the vertex are the same as a previously computed vertex. If predetermined lighting properties are the same as the previously computed vertex, then the method retrieves at least one preprocessed value from a storage location; and utilizes the at least one preprocessed value to compute the vertex color. If, however, the predetermined lighting properties are not the same as the previously computed vertex, then the method computes at least one preprocessed value from the received lighting properties of the primitive vertex, stores the at least one computed preprocessed value in a storage location, and utilizes the at least one preprocessed value to compute the vertex color. The system includes at least one processing unit (e.g.Type: GrantFiled: April 30, 1997Date of Patent: September 21, 1999Assignee: Hewlett-Packard Co.Inventors: S Paul Tucker, Alan S. Krech, Jr.