Abstract: A computer system for controlling virtual machines each given a different identification number. The system comprises mask registers and I/O interruption queues, each provided with the same numbers as the virtual machines, and corresponding to any one of the identification numbers. An interrupt handling in any one of the virtual machines can be carried out directly by using a pair of corresponding mask registers and I/O interruption queues without an interposition of the VM monitor.

Abstract: A virtual machine system having a virtual storage function, wherein registers are provided for holding the heading and trailing addresses of the continuous area in the main storage area assigned respectively for each of the plural operating systems. When the main storage area is accessed by a channel or sub-channel, one of the registers is selected, and the heading address of the register selected is added to the main storage address sent from the channel or sub-channel. The added main storage address is compared with the trailing address in the selected register and if the former is smaller than the latter, the overhead for supporting the virtual storage area is reduced by accessing the main storage area in accordance with the added main storage address mentioned above.

Abstract: A communication system operation between computer systems which realizes highly efficient data transfer in a data processing system has sender and receiver subsystems operating under the control of an independent or common operating system. The communication system also includes: a plurality of sending buffers, a sending buffer address table having a plurality of entries and a buffer control block in the sender subsystem and a plurality of receiving buffers, a receiving buffer address table having a plurality of entries and a buffer control block in the receiver subsystem, and the communication path for transferring the data stored in the sending buffer to the receiving buffer.

Abstract: A virtual machine system is provided with a control program for concurrently operating a plurality of OSs (Operating Systems). The object is to suppress the overhead produced when simulating privileged instructions for controlling program status words (PSWs). For this purpose, there is provided simple hardware, in place of the software control conventionally used, including a modification register for storing information required to modify the current PSW information and a pending register for storing pending interrupt information for communication to the corresponding OS.

Abstract: An address control system for software simulation in a virtual machine system having a virtual storage function. When a simulator program is simulating an instruction of a program to be simulated, an address translation of an operand address in the program to be simulated is achieved using a translation lookaside buffer, thereby greatly reducing the overhead for the address translation during the simulator program execution.

Abstract: A data register storing an instruction code field, modification bits, a control bit field, condition branching fields and the next address in corresponding areas thereof is coupled to a control memory via a plurality of AND gates. A branch determination circuit for determining an instruction for selecting in accordance with a machine state, a single micro-instruction of four which are read out from the control memory, is connected to each AND gate for controlling them. The branch determination circuit is connected to the data register's condition branching field areas. A save-restore address register storing the address and branch address bits in corresponding areas thereof is coupled to the data register's next address area, the branch determination circuit, the control memory, from a first branch address bit area thereof to each AND gate for controlling them and is connected to a first bit modification control circuit.

Abstract: An access control unit for controlling a memory device having a plurality of memory units for storing data in a manner whereby the memory units are accessed sequentially, comprises a data register for storing data read out from the memory device, a cycle designation device for indicating in every cycle the memory unit of the memory device to be accessed in the relevant cycle, an address device for providing in each cycle an address to the memory unit indicated by the cycle designation device, a non-coincidence detection circuit for detecting non-coincidence between the memory unit indicated by the address and the memory unit practically provided with that address, and an invalidating device utilizing the output of the non-coincidence detection circuit for invalidating data read out from the memory device in a cycle a specified number of cycles after that in which non-coincidence is detected.