Patents by Inventor Sachiaki TEZUKA

Sachiaki TEZUKA has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250081424
    Abstract: A semiconductor device that can be highly integrated is provided. The semiconductor device includes first and second transistors. The first transistor includes a semiconductor layer, a pair of first conductive layers, and a pair of second conductive layers over the pair of first conductive layers. The pair of first conductive layers and the pair of second conductive layers function as a source electrode and a drain electrode of the first transistor. A third conductive layer functioning as a gate electrode of the second transistor is in contact with one of the pair of first conductive layers. In a cross-sectional view of the first transistor in the channel width direction, the height of the semiconductor layer is larger than the width of the semiconductor layer. The semiconductor device can include a capacitor, in which the third conductive layer also functions as one of a pair of electrodes.
    Type: Application
    Filed: August 27, 2024
    Publication date: March 6, 2025
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tsutomu MURAKAWA, Hiromi SAWAI, Motomu KURATA, Sachiaki TEZUKA, Jun YAMADA, Shunpei YAMAZAKI
  • Patent number: 12191399
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: April 19, 2023
    Date of Patent: January 7, 2025
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20240429319
    Abstract: A semiconductor device having favorable electrical characteristics is provided.
    Type: Application
    Filed: August 28, 2024
    Publication date: December 26, 2024
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Jun ISHIKAWA, Sachiaki TEZUKA, Tetsuya KAKEHATA
  • Patent number: 12094979
    Abstract: A semiconductor device having favorable electrical characteristics is provided.
    Type: Grant
    Filed: October 17, 2019
    Date of Patent: September 17, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Yasuhiro Jinbo, Jun Ishikawa, Sachiaki Tezuka, Tetsuya Kakehata
  • Publication number: 20240304728
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: April 18, 2024
    Publication date: September 12, 2024
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 11967649
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: August 25, 2022
    Date of Patent: April 23, 2024
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20230361219
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: April 19, 2023
    Publication date: November 9, 2023
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Publication number: 20230326955
    Abstract: A semiconductor device with a small variation in characteristics is provided. In a manufacturing method of a semiconductor device including a capacitor with reduced leak current, a first conductor is formed; a second insulator is formed over the first conductor; a third insulator is formed over the second insulator; a second conductor is formed over the third insulator; a fourth insulator is deposited over the second conductor and the third insulator; by heat treatment, hydrogen contained in the third insulator diffuses into or is absorbed by the second insulator; the first conductor is one electrode of the capacitor; the second conductor is the other electrode of the capacitor; and each of the second insulator and the third insulator is a dielectric of the capacitor.
    Type: Application
    Filed: August 12, 2021
    Publication date: October 12, 2023
    Inventors: Shunpei YAMAZAKI, Sachiaki TEZUKA, Haruyuki BABA, Yuji EGI, Yasuhiro JINBO, Yujiro SAKURADA, Takeshi AOKI
  • Patent number: 11646378
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: February 4, 2021
    Date of Patent: May 9, 2023
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20220416089
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: August 25, 2022
    Publication date: December 29, 2022
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 11495691
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Grant
    Filed: May 27, 2019
    Date of Patent: November 8, 2022
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Takeuchi, Naoto Yamade, Yutaka Okazaki, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20210399134
    Abstract: A semiconductor device having favorable electrical characteristics is provided.
    Type: Application
    Filed: October 17, 2019
    Publication date: December 23, 2021
    Inventors: Shunpei YAMAZAKI, Yasuhiro JINBO, Jun ISHIKAWA, Sachiaki TEZUKA, Tetsuya KAKEHATA
  • Publication number: 20210210640
    Abstract: The semiconductor device includes a first conductor and a second conductor; a first insulator to a third insulator; and a first oxide to a third oxide. The first conductor is disposed to be exposed from a top surface of the first insulator. The first oxide is disposed over the first insulator and the first conductor. A first opening reaching the first conductor is provided in the first oxide. The second oxide is disposed over the first oxide. The second oxide comprises a first region, a second region, and a third region positioned between the first region and the second region. The third oxide is disposed over the second oxide. The second insulator is disposed over the third oxide. The second conductor is disposed over the second insulator. The third insulator is disposed to cover the first region and the second region and to be in contact with the top surface of the first insulator.
    Type: Application
    Filed: May 27, 2019
    Publication date: July 8, 2021
    Inventors: Toshihiko TAKEUCHI, Naoto YAMADE, Yutaka OKAZAKI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Publication number: 20210184042
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Application
    Filed: February 4, 2021
    Publication date: June 17, 2021
    Inventors: Tetsuhiro TANAKA, Mitsuhiro ICHIJO, Toshiya ENDO, Akihisa SHIMOMURA, Yuji EGI, Sachiaki TEZUKA, Shunpei YAMAZAKI
  • Patent number: 10950734
    Abstract: A semiconductor device includes a semiconductor, a first conductor, a second conductor, a third conductor, a fourth conductor, a first insulator, a second insulator, a third insulator, and a fourth insulator. The first conductor and the semiconductor partly overlap with each other with the first insulator positioned therebetween. The second conductor and the third conductor have regions in contact with the semiconductor. The semiconductor has a region in contact with the second insulator. The fourth insulator has a first region and a second region. The first region is thicker than the second region. The first region has a region in contact with the second insulator. The second region has a region in contact with the third insulator. The fourth conductor and the second insulator partly overlap with each other with the fourth insulator positioned therebetween.
    Type: Grant
    Filed: January 16, 2019
    Date of Patent: March 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Publication number: 20210073610
    Abstract: A thin film manufacturing apparatus capable of forming thin films with high uniformity is provided. A thin film manufacturing apparatus capable of controlling various kinds of set conditions during thin film formation is provided. The thin film manufacturing apparatus includes a treatment chamber, a gas supply means, an evacuation means, an electric power supply means, an arithmetic portion, and a control device; the gas supply means supplies gas into the treatment chamber; the evacuation means adjusts a pressure in the treatment chamber; the electric power supply means applies voltage between electrodes provided in the treatment chamber; the arithmetic portion has a function of performing detection of an abnormal state and inference with the use of a neural network during thin film formation; and the control device controls various kinds of set conditions in accordance with results of the detection and the inference during the thin film formation.
    Type: Application
    Filed: December 18, 2018
    Publication date: March 11, 2021
    Inventors: Kazutaka KURIKI, Sachiaki TEZUKA, Kouhei TOYOTAKA
  • Patent number: 10923600
    Abstract: A transistor with stable electrical characteristics. A semiconductor device includes a first insulator over a substrate, a second insulator over the first insulator, an oxide semiconductor in contact with at least part of a top surface of the second insulator, a third insulator in contact with at least part of a top surface of the oxide semiconductor, a first conductor and a second conductor electrically connected to the oxide semiconductor, a fourth insulator over the third insulator, a third conductor which is over the fourth insulator and at least part of which is between the first conductor and the second conductor, and a fifth insulator over the third conductor. The first insulator contains a halogen element.
    Type: Grant
    Filed: July 25, 2018
    Date of Patent: February 16, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Mitsuhiro Ichijo, Toshiya Endo, Akihisa Shimomura, Yuji Egi, Sachiaki Tezuka, Shunpei Yamazaki
  • Publication number: 20200135445
    Abstract: A semiconductor device having favorable electrical characteristics is provided. A first insulator is formed over an oxide, a second insulator is formed over the first insulator, a conductor is formed over the second insulator, and a third insulator that is in contact with a top surface of the oxide, a side surface of the first insulator, a side surface of the second insulator, and a side surface of the conductor is formed. The first insulator and the second insulator are successively formed in a reduced-pressure atmosphere.
    Type: Application
    Filed: April 16, 2018
    Publication date: April 30, 2020
    Applicant: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Shunpei YAMAZAKI, Sachiaki TEZUKA, Hiroki KOMAGATA, Yuji EGI, Naoki OKUNO
  • Patent number: 10522397
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Grant
    Filed: March 15, 2019
    Date of Patent: December 31, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Yuta Endo, Hideomi Suzawa, Sachiaki Tezuka, Tetsuhiro Tanaka, Toshiya Endo, Mitsuhiro Ichijo
  • Publication number: 20190237586
    Abstract: A miniaturized transistor is provided. A first layer is formed over a third insulator over a semiconductor; a second layer is formed over the first layer; an etching mask is formed over the second layer; the second layer is etched using the etching mask until the first layer is exposed to form a third layer; a selective growth layer is formed on a top surface and a side surface of the third layer; the first layer is etched using the third layer and the selective growth layer until the third insulator is exposed to form a fourth layer; and the third insulator is etched using the third layer, the selective growth layer, and the fourth layer until the semiconductor is exposed to form a first insulator.
    Type: Application
    Filed: March 15, 2019
    Publication date: August 1, 2019
    Inventors: Yuta ENDO, Hideomi SUZAWA, Sachiaki TEZUKA, Tetsuhiro TANAKA, Toshiya ENDO, Mitsuhiro ICHIJO