Abstract: An information processor comprises an instruction decoder for executing a subroutine calling instruction including designation of a general-purpose register for calling a subroutine, a circuit for selecting a specific general-purpose register designated by an instruction based on a result of the execution of a subroutine calling instruction among a plurality of general-purpose registers, and a circuit for saving, in a selected general-purpose register, a value obtained by adding a length of a subroutine calling instruction to a program counter value as a return address.

Abstract: A data processing system includes an instruction decoder for decoding a string of instructions including an arithmetic operation instruction, an arithmetic operation unit controlled by the instruction decoder for executing a designated arithmetic operation for a received data, the arithmetic operation unit outputting not only the result of the designated arithmetic operation, but also a sign information and an overflow/underflow information of the result of the designated arithmetic operation, and a saturation detecting circuit receiving the sign information and the overflow/underflow information for controlling a selector in such a manner that if an overflow has occurred when the sign information indicates the positive, the selector selects a positive maximum value; if an underflow has occurred when the sign information indicates the negative, the selector selects a negative maximum value; and if neither the overflow nor the underflow has occurred, the selector selects the result of arithmetic operation outp

Abstract: In an interrupt controller, interrupt processing mode indication circuits are provided for each interrupt request circuit for storing interrupt processing mode information, and priority level indication circuits are provided for each interrupt request circuit, for storing acknowledgement order information. A search information generating circuit is provided each for generating interrupt processing mode search information and priority order search information. A search information comparison circuit detects the state of the interrupt request circuit provided for each interrupt request memory circuit, and compares the processing mode information and the acknowledgement order information with the interrupt processing mode search information and priority order search information.