Abstract: An apparatus is provided having a memory device and associated access control circuitry, and an additional memory device and associated additional access control circuitry. Redundant data generation circuitry generates, for a given block of data having an associated given memory address, an associated block of redundant data for use in an error detection process. The access control circuitry is arranged to store, at a location in the memory device determined from the given memory address, at least a portion of the given block of data and a first copy of the associated block of redundant data, and the additional access control circuitry is arranged to store, at a location in the additional memory device determined from the given memory address, any remaining portion of the given block of data not stored in the memory device and a second copy of the associated block of redundant data.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to supply the charge dependent on at least one of the temperature of the memory circuit and the potential difference supply of the memory circuit.

Abstract: A memory circuit includes a memory cell configured to be re-writable. A write enable circuit is configured to enable writing a signal via a pair of bit lines to the memory cell depending on a write signal. A charge supply circuit is configured to supply a charge to at least one of the pair of bit lines. A charge supply controller is configured to control the charge supply circuit to disable the supply of charge and couple the write enable circuit to at least one of the pair of bit lines after a first determined period following the reception of the write signal.