Patents by Inventor Sadahiro Kato
Sadahiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8884393Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.Type: GrantFiled: July 10, 2013Date of Patent: November 11, 2014Assignee: Furukawa Electric Co., Ltd.Inventors: Takuya Kokawa, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
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Publication number: 20140084298Abstract: A nitride compound semiconductor device includes: a substrate; a buffer layer formed on the substrate and including a plurality of composite layers each layered of: a first layer formed of a nitride compound semiconductor; and a second layer formed of a nitride compound semiconductor containing aluminum and having a lattice constant smaller than a lattice constant of the first layer; a semiconductor operating layer formed on the buffer layer; and a plurality of electrodes formed on the semiconductor operating layer. At least one of the second layers has oxygen added therein.Type: ApplicationFiled: July 10, 2013Publication date: March 27, 2014Inventors: Takuya KOKAWA, Tatsuyuki Shinagawa, Masayuki Iwami, Kazuyuki Umeno, Sadahiro Kato
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Patent number: 8569800Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recess.Type: GrantFiled: March 31, 2011Date of Patent: October 29, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
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Patent number: 8450782Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.Type: GrantFiled: March 30, 2011Date of Patent: May 28, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Yoshihiro Sato, Takehiko Nomura, Nariaki Ikeda, Takuya Kokawa, Masayuki Iwami, Sadahiro Kato
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Patent number: 8421182Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.Type: GrantFiled: December 16, 2009Date of Patent: April 16, 2013Assignee: Furukawa Electric Co., Ltd.Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
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Patent number: 8338859Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and smaller coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area tType: GrantFiled: September 29, 2009Date of Patent: December 25, 2012Assignee: Furukawa Electric Co., LtdInventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
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Patent number: 8309988Abstract: Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 8 is provided on the bottom surface or the top surface of the field effect transistor. When the body electrode 8 is provided on the bottom surface, a p-type GaN layer 4 is provided on a p-type Si substrate 2 via a buffer layer 3 comprising a plurality of AlN layers 31 and GaN layers 32, with the top layer of that buffer layer 3 being a thin AlN layer 31, and the body electrode 8 being formed on the bottom surface of the p-type Si substrate. When the body electrode 8 is provided on the top surface, a p-type GaN layer 4 is provided on a sapphire substrate 21 and an AlGaN layer 13 is provided on the area under the source electrode 5 and drain electrode 6, with the body electrode 8 being provided on top of the AlGaN layer 13. Holes 20 that are generated by an avalanche phenomenon run through the body electrode 8.Type: GrantFiled: March 26, 2010Date of Patent: November 13, 2012Assignee: Furukawa Electric Co., LtdInventors: Yuki Niiyama, Takehiko Nomura, Sadahiro Kato
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Patent number: 8304809Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.Type: GrantFiled: November 13, 2008Date of Patent: November 6, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Koh Li
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Patent number: 8134181Abstract: A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.Type: GrantFiled: August 12, 2009Date of Patent: March 13, 2012Assignee: Furukawa Electric Co., Ltd.Inventors: Yoshihiro Sato, Sadahiro Kato, Seikoh Yoshida
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Patent number: 8067787Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a tType: GrantFiled: February 3, 2009Date of Patent: November 29, 2011Assignee: The Furukawa Electric Co., LtdInventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
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Publication number: 20110241017Abstract: A field effect transistor includes: a buffer layer that is formed on a substrate; a high resistance layer or a foundation layer that is formed on the buffer layer; a carbon-containing carrier concentration controlling layer that is formed on the high resistance layer or the foundation layer; a carrier traveling layer that is formed on the carrier concentration controlling layer; a carrier supplying layer that is formed on the carrier traveling layer; a recess that is formed from the carrier supplying layer up to a predetermined depth; source/drain electrodes that are formed on the carrier supplying layer with the recess intervening therebetween; a gate insulating film that is formed on the carrier supplying layer so as to cover the recess; and a gate electrode that is formed on the gate insulating film in the recessType: ApplicationFiled: March 31, 2011Publication date: October 6, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
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Publication number: 20110241088Abstract: A field effect transistor includes a high resistance layer on a substrate, a semiconductor operation layer that is formed on the high resistance layer and includes a channel layer that has the carbon concentration of not more than 1×1018 cm?3 and has the layer thickness of more than 10 nm and not more than 100 nm, a recess that is formed up to the inside of the channel layer in the semiconductor operation layer, source and drain electrodes that are formed on the semiconductor operation layer with the recess intervening therebetween, a gate insulating film that is formed on the semiconductor operation layer so as to cover the recess, and a gate electrode that is formed on the gate insulating film in the recess.Type: ApplicationFiled: March 30, 2011Publication date: October 6, 2011Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Yoshihiro SATO, Takehiko NOMURA, Nariaki IKEDA, Takuya KOKAWA, Masayuki IWAMI, Sadahiro KATO
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Patent number: 7943496Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.Type: GrantFiled: February 17, 2010Date of Patent: May 17, 2011Assignee: Furukawa Electric Co., Ltd.Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
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Patent number: 7812371Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.Type: GrantFiled: March 5, 2009Date of Patent: October 12, 2010Assignee: Furukawa Electric Co., Ltd.Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama
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Publication number: 20100244097Abstract: Provided is a GaN based field effect transistor that is capable of normally-off operation, high breakdown voltage and large current. A body electrode 8 is provided on the bottom surface or the top surface of the field effect transistor. When the body electrode 8 is provided on the bottom surface, a p-type GaN layer 4 is provided on a p-type Si substrate 2 via a buffer layer 3 comprising a plurality of AlN layers 31 and GaN layers 32, with the top layer of that buffer layer 3 being a thin AlN layer 31, and the body electrode 8 being formed on the bottom surface of the p-type Si substrate. When the body electrode 8 is provided on the top surface, a p-type GaN layer 4 is provided on a sapphire substrate 21 and an AlGaN layer 13 is provided on the area under the source electrode 5 and drain electrode 6, with the body electrode 8 being provided on top of the AlGaN layer 13. Holes 20 that are generated by an avalanche phenomenon run through the body electrode 8.Type: ApplicationFiled: March 26, 2010Publication date: September 30, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Yuki Niiyama, Takehiko Nomura, Sadahiro Kato
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Publication number: 20100213577Abstract: A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper lType: ApplicationFiled: February 25, 2010Publication date: August 26, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami, Takuya Kokawa
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Publication number: 20100210080Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.Type: ApplicationFiled: February 17, 2010Publication date: August 19, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
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Publication number: 20100127307Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.Type: ApplicationFiled: December 16, 2009Publication date: May 27, 2010Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
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Publication number: 20100078678Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area tType: ApplicationFiled: September 29, 2009Publication date: April 1, 2010Applicant: FURUKAWA ELECTRIC CO., LTD.Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
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Patent number: 7679104Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.Type: GrantFiled: November 8, 2007Date of Patent: March 16, 2010Assignee: The Furukawa Electric Co., Ltd.Inventors: Yoshihiro Sato, Sadahiro Kato, Masayuki Iwami, Hitoshi Sasaki, Shinya Ootomo, Yuki Niiyama