Patents by Inventor Sadahiro Kato

Sadahiro Kato has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20100213577
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer that comprises composite laminations of which a first semiconductor layer, that is formed of a compound semiconductor of a nitride system, that has a lattice constant to be as smaller than that of such the substrate, and that has a coefficient of thermal expansion to be as larger than that of such the substrate, and a second semiconductor layer that is formed of a compound semiconductor of a nitride system are formed as alternately on to such the substrate; a semiconductor operation layer that is formed of a compound semiconductor of a nitride system and that is formed on to such the buffer layer; and a dislocation reduction layer, which comprises a lower layer region and an upper layer region that are formed at any location at an inner side of such the buffer layer and that comprise an interface of a concave and convex shape therebetween, at which a threading dislocation that draws from such the lower layer region toward such the upper l
    Type: Application
    Filed: February 25, 2010
    Publication date: August 26, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami, Takuya Kokawa
  • Publication number: 20100210080
    Abstract: A method of manufacturing a GaN-based field effect transistor is provided by which a lower resistance and a higher breakdown voltage are obtained and which is less affected by a current collapse.
    Type: Application
    Filed: February 17, 2010
    Publication date: August 19, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Takehiko Nomura, Nariaki Ikeda, Shusuke Kaya, Sadahiro Kato
  • Publication number: 20100127307
    Abstract: A semiconductor layer of a second conductive type is formed on a RESURF layer of a first conductive type that is formed on a buffer layer. A contact layer of the first conductive type is formed in or on the semiconductor layer. A source electrode is formed on the contact layer. A drain electrode is formed on the RESURF layer. A gate insulating film is formed on the semiconductor layer to overlap with an end of the semiconductor layer. A gate electrode is formed on the gate insulating film to overlap with the end of the semiconductor layer. A channel formed near the end of the semiconductor layer is electrically connected to the RESURF layer.
    Type: Application
    Filed: December 16, 2009
    Publication date: May 27, 2010
    Inventors: Takehiko Nomura, Seikoh Yoshida, Sadahiro Kato
  • Publication number: 20100078678
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on said substrate, having two or more layers of composite layers in which a first semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the substrate and a second semiconductor layer comprising nitride based compound semiconductor having smaller lattice constant and greater coefficient of thermal expansion than the first semiconductor layer are alternately laminated; a semiconductor operating layer comprising nitride based compound semiconductor formed on said buffer layer; a dislocation reducing layer comprising nitride based compound semiconductor, formed in a location between a location directly under said buffer layer and inner area of said semiconductor operating layer, and comprising a lower layer area and an upper layer area each having an uneven boundary surface, wherein threading dislocation extending from the lower layer area t
    Type: Application
    Filed: September 29, 2009
    Publication date: April 1, 2010
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Patent number: 7679104
    Abstract: A vertical semiconductor element comprises: an electro-conductive substrate; a GaN layer, as a nitride compound semiconductor layer, which is selectively grown as a convex shape on one surface of the electro-conductive substrate through a buffer layer; a source electrode as a first electrode formed on the GaN layer; and a drain electrode as a second electrode formed on another surface of the electro-conductive substrate.
    Type: Grant
    Filed: November 8, 2007
    Date of Patent: March 16, 2010
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Yoshihiro Sato, Sadahiro Kato, Masayuki Iwami, Hitoshi Sasaki, Shinya Ootomo, Yuki Niiyama
  • Publication number: 20100032716
    Abstract: A semiconductor device includes a substrate; a buffer layer; and a compound semiconductor layer laminated on the substrate with the buffer layer in between. The buffer layer has a dislocation density in a plane in parallel to an in-plane direction thereof, so that a volume resistivity of the buffer layer becomes a substantially maximum value.
    Type: Application
    Filed: August 12, 2009
    Publication date: February 11, 2010
    Inventors: Yoshihiro Sato, Sadahiro Kato, Seikoh Yoshida
  • Publication number: 20090278172
    Abstract: The field effect transistor includes a laminated structure in which a buffer layer, and an electron transporting layer (undoped GaN layer), and an electron supplying layer (undoped AlGaN layer) are laminated in sequence on a sapphire substrate. An npn laminated structure is formed on a source region of the electron supplying layer, and a source electrode is formed on the npn laminated structure. A drain electrode is formed in a drain region of the electron supplying layer, and an insulating film is formed in an opening region formed in the gate region. When a forward voltage greater than a threshold is applied to the gate electrode, an inversion layer is formed and the drain current flows. By changing a thickness and an impurity concentration of the p-type GaN layer, the threshold voltage can be controlled. The electrical field concentration between the gate electrode and the drain electrode is relaxed due to the drift layer, and voltage resistance improves.
    Type: Application
    Filed: March 5, 2009
    Publication date: November 12, 2009
    Inventors: Shusuke Kaya, Seikoh Yoshida, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama, Masatoshi Ikeda
  • Publication number: 20090200645
    Abstract: A semiconductor electronic device comprises a substrate; a buffer layer formed on the substrate, the buffer layer including not less than two layers of composite layer in which a first semiconductor layer formed of a nitride-based compound semiconductor layer having a lattice constant smaller than a lattice constant of the substrate and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate and a second semiconductor layer formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a thermal expansion coefficient of the substrate are alternately laminated; an intermediate layer provided between the substrate and the buffer layer, the intermediate layer being formed of a nitride-based compound semiconductor having a lattice constant smaller than a lattice constant of the first semiconductor layer and a thermal expansion coefficient larger than a t
    Type: Application
    Filed: February 3, 2009
    Publication date: August 13, 2009
    Applicant: The Furukawa Electric Co., LTD.
    Inventors: Takuya Kokawa, Sadahiro Kato, Yoshihiro Sato, Masayuki Iwami
  • Publication number: 20090140295
    Abstract: A GaN-based semiconductor device includes a silicon substrate; an active layer of a GaN-based semiconductor formed on the silicon substrate; a trench formed in the active layer and extending from a top surface of the active layer to the silicon substrate; a first electrode formed on an internal wall surface of the trench so that the first electrode extends from the top surface of the active layer to the silicon substrate; a second electrode formed on the active layer so that a current flows between the first electrode and the second electrode via the active layer; and a bottom electrode formed on a bottom surface of the silicon substrate. The first electrode is formed of a metal capable of being in ohmic contact with the silicon substrate and the active layer.
    Type: Application
    Filed: November 13, 2008
    Publication date: June 4, 2009
    Inventors: Shusuke Kaya, Seikoh Yoshida, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Koh Li
  • Publication number: 20080142837
    Abstract: A vertical semiconductor element comprises: an electro-conductive substrate 1; a GaN layer 3, as a nitride compound semiconductor layer, which is selectively grown as convex shape on an one surface of the electro-conductive substrate 1 through a buffer layer 9; a source electrode 25 as a first electrode formed on the GaN layer 3; and a drain electrode 29 as a second electrode formed on another surface of the electro-conductive substrate 1.
    Type: Application
    Filed: November 8, 2007
    Publication date: June 19, 2008
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshihiro Sato, Sadahiro Kato, Masayuki Iwami, Hitoshi Sasaki, Shinya Ootomo, Yuki Niiyama
  • Publication number: 20070045639
    Abstract: A semiconductor electronic device includes a buffer layer formed on a substrate, and a semiconductor operating layer that is formed on the buffer layer. The semiconductor operating layer includes a nitride-based compound semiconductor and. The buffer layer includes at least one composite layer that includes a first layer and a second layer. A lattice-constant difference between the first layer and the second layer is equal to or more than 0.2 percent.
    Type: Application
    Filed: August 24, 2006
    Publication date: March 1, 2007
    Applicant: THE FURUKAWA ELECTRIC CO., LTD.
    Inventors: Sadahiro Kato, Yoshihiro Sato, Seikoh Yoshida