Abstract: A method of designing a semiconductor integrated circuit includes steps of selecting a pair of scan registers to be connected as a scan chain and calculating a beeline distance on hardware from each output terminal of the scan register at the front stage to a scan data input terminal of the scan register at the rear stage. The method further includes steps of selecting the output terminal of the scan register at the front stage having a minimum beeline distance on the basis of the above calculation; determining to connect the selected output terminal with the scan data input terminal of the scan register at the rear stage; and forming the scan chain by connecting each pair of scan registers by using the output terminal determined in the previous step.

Abstract: A semiconductor IC includes a test circuit comprising a logic circuit, a test timing generator, a first register serving as a test signal generation point, and second and third registers serving as test signal observation points. In this test circuit, a target signal transmission path to be tested is selected from a plurality of signal transmission paths in the logic circuit, and the test timing generator outputs a test clock having a cycle according to a delay time of the selected signal transmission path on design to the first to third registers, whereby the first register generates a test signal and the second and third registers observe the test signal. Therefore, the signal transmission paths connecting the test signal generation point and the test signal observation point are tested with high efficiency, whereby more signal transmission paths are tested for delay faults with less number of times the test is executed.

Abstract: In a semiconductor integrated circuit, a select signal output circuit switches a selector to take in the output of a circuit section in response to a signal “0” received at the D terminal thereof during normal operation. Thus, a scan flip-flop receives the output of the circuit section. During a scan test mode, a select signal “0” or “1” is input through a scan-in terminal to the select signal output circuit and then to the selector. If the select signal is “0”, then the selector selects the output of the circuit section. On the other hand, if the select signal is “1”, then the selector selects a clock signal supplied from a clock signal generator. The output of the circuit section or the clock signal supplied from the clock signal generator, which has been input to the scan flip-flop, is passed through a scan path and output to the outside through a scan-out terminal.

Abstract: In an apparatus for generating a test pattern for a sequential logic circuit including a plurality of storage elements each storage element storing a logical value of one bit wherein logical values of bits of the plurality of storage elements being represented by a state, first external input values are generated so that a transition process is performed from a second state of the plurality of storage elements to a first state thereof, and second external input values are generated so hat a transition process is performed from a third state of the plurality of storage elements to the first state thereof. Thereafter, third external input values are generated so that a transition process is performed from a fourth state of the plurality of storage elements to the first state thereof. After setting the fourth state as the first state, name data of storage elements corresponding to bits of different states between the second and third states are stored in a storage unit.