Abstract: A level shifter removes delay, which is generated at the time of transition of an input signal level, by adjusting a size of NMOS transistors to perform pull-down and pull-up operations. The level shifter includes a coupling unit for setting up a voltage level of a first node according to a voltage level of an input signal, a first buffer for transferring an output signal by buffering a signal from the first node, and a driving unit configured to receive the input signal and the output signal and drive the first node.

Abstract: A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether general cells corresponding to input addresses are repaired or not and activate the redundant cells, decoding units configured to decode a refresh address or a normal address and activate the general cells or the redundant cells according to the decoded refresh address or normal address, and a control unit configured to perform control such that the addresses, which are output by the decoding units, are not input to the repair sets according to a control signal.

Abstract: A block repair apparatus includes a plurality of cell blocks, a block repair fuse, a block isolation control unit, and a block repair selector. The block repair fuse outputs a repair signal of the plurality of cell blocks. The block isolation control unit outputs a control signal for activating the plurality of cell blocks or electrically isolating a defective cell block of the plurality of cell blocks, in response to the block repair signal. The block repair selector outputs a block repair selection signal for replacing the defective cell block with another cell block in response to a cell block address signal.

Abstract: A semiconductor memory device includes: a plurality of error correction code (ECC) groups, each ECC group including plural data configured to be read from and written to the semiconductor memory device and plural parity data configured to correct an error of the plural data, wherein at least one of the ECC groups includes the plural data allocated in dispersed memory cells, not adjacent.

Abstract: A semiconductor memory device includes: a plurality of cell array blocks; a boosted voltage driving unit for selectively supplying a boosted voltage to the cell array blocks; and a controller controlling a driving operation of the boosted voltage driving unit in response to a cell array block select signal.

Abstract: A semiconductor memory apparatus configured to have general cells and redundant cells for repairing defective cells among the general cells includes; repair sets configured to determine whether general cells corresponding to input addresses are repaired or not and activate the redundant cells, decoding units configured to decode a refresh address or a normal address and activate the general cells or the redundant cells according to the decoded refresh address or normal address, and a control unit configured to perform control such that the addresses, which are output by the decoding units, are not input to the repair sets according to a control signal.

Abstract: A method for driving a semiconductor memory device, includes initializing first data corresponding to a refresh time of each corresponding row included in a cell array; storing second data corresponding to column data included in the first row after entering a self refresh mode; setting the first data corresponding to the first row by detecting the refresh time of the first row while performing refresh operations on the other rows in the cell array according to a refresh period selected based on the corresponding first data for predetermined refresh cycles, wherein the refresh operation is not performed on the first row during the predetermined refresh cycles; restoring the second data to the first row; and repeating the above steps for the other rows to thereby set the corresponding first data until the setting step is completed for all rows or the self refresh mode expires.

Abstract: An internal voltage generation apparatus for a semiconductor device is disclosed. The internal voltage generation apparatus includes a power-up detector for receiving an external supply voltage and generating a power-up signal, an internal voltage generator for generating a plurality of internal voltages, and an initial level holder including a plurality of transistors for supplying the external supply voltage to the internal voltage generator in response to the power-up signal, and a plurality of passive elements connected in parallel with the transistors, respectively.

Abstract: A temperature detector includes a pulse generator adapted to generate pulse signals based on temperature detecting signals, a first delay circuit adapted to delay the temperature detecting signals in accordance with different delay times and generate a plurality of first delayed signals, a second delay circuit adapted to delay the temperature detecting signals and generate a plurality of second delayed signals, a plurality of detectors adapted to compare the plurality of first delayed signals from the first delay circuit and the plurality of second delayed signals from the second delay circuit and generate compared values based on the pulse signals, a plurality of pads adapted to read outputs generated by the plurality of detectors, and a comparison unit adapted to compare temperature values read from the plurality of pads and current temperature values to determine an optimum detector that generates an optimum temperature value.

Abstract: A temperature detector includes a pulse generator adapted to generate pulse signals based on temperature detecting signals, a first delay circuit adapted to delay the temperature detecting signals in accordance with different delay times and generate a plurality of first delayed signals, a second delay circuit adapted to delay the temperature detecting signals and generate a plurality of second delayed signals, a plurality of detectors adapted to compare the plurality of first delayed signals from the first delay circuit and the plurality of second delayed signals from the second delay circuit and generate compared values based on the pulse signals, a plurality of pads adapted to read outputs generated by the plurality of detectors, and a comparison unit adapted to compare temperature values read from the plurality of pads and current temperature values to determine an optimum detector that generates an optimum temperature value.

Abstract: The present invention discloses a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor. When data of the memory cell selected by a received address in a read operation according to a first command signal are outputted through a data output pad, if a second command signal is inputted, address and data are stored in registers, an operation is performed according to the second command signal, and then the read operation is carried out by using the address and data stored in the registers.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: The present invention discloses a virtual static random access memory device that uses a dynamic memory cell and refreshes data of the memory cell, and a driving method therefor. When data of the memory cell selected by a received address in a read operation according to a first command signal are outputted through a data output pad, if a second command signal is inputted, address and data are stored in registers, an operation is performed according to the second command signal, and then the read operation is carried out by using the address and data stored in the registers.

Abstract: A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a reliability of the apparatus, and reduces the power-consumption.

Abstract: A multi-bit counter of the present invention is capable of high-speed operation because the time needed for increasing count values and combining count bits for a carry can be minimized by presetting all bit combinations for a unit having multiple bits and selecting the preset combinations by a clock signal, i.e., by presetting the state of each of the bit combinations and outputting a next required value.

Abstract: The present invention discloses a delay circuit having a constant delay time. The delay circuit comprises an electric wire for transmitting a driving signal from a driver; a capacitor connected between said electric wire and ground, and for delaying transmission of said driving signal; and a current source connected to said electric wire and capacitor in parallel, and for keeping an amount of an electric current applied to said capacitor constant when a signal applied to said capacitor is varied.

Abstract: A data register circuit, comprising: input means which includes a first input portion and a second input portion, the first input portion being reset by a data reset signal and buffering a data signal from a data line in accordance with a data fetch signal and the second input portion being reset by a data reset signal and buffering a data bar signal from a data bar line in accordance with the data fetch signal; storing means which includes a first flip flop and a second flip flop, the first and second flip flops for respectively receiving output signals of the first and second input portions of the input means and providing inverting signals of the output signals of the first and second input portions until the output signals of the first and second input portions are changed by the data reset signal, a first latch which is connected between the first input portion and the first flip flop and temporarily stores the output signal of the first input portion and a second latch which is connected between the sec

Abstract: The present invention discloses a method and a device for automatically performing a refresh operation, which can reduce power consumption in an auto refresh mode of a semiconductor memory device. The power consumption can be reduced by controlling the operation of input buffers or the operation of an input buffer generator for controlling the input buffers, during the auto refresh operation.

Abstract: A multi-driving apparatus by a multi-level detection which pluralizes a voltage detection level in order to effectively operate voltage generators in the voltage generation circuit, minimizes a level fluctuation, reduces noise influenced on a total operation of the apparatus, increases a reliability of the apparatus, and reduces the power-consumption.

Abstract: The voltage control generator for a semiconductor device is disclosed, in which the substrate bias voltage through the oscillation period of the step-up voltage generator circuit are quickly adjusted with respect to the level variation of a corresponding voltage. The circuit according to the present invention includes a control level generator generating at least one control signal for detecting a substrate bias voltage level from a substrate of a semiconductor device and adjusting the width of an oscillation period to a set level in accordance with the detected signal, a voltage control oscillator generating a signal in which the width of an oscillation period is varied to the set level in response to an output signal from the control level generator, and a charge pump supplying a stable bias voltage to the substrate of the semiconductor device by increasing or decreasing a pumping speed in response to an output signal from the voltage control oscillator.