Patents by Inventor Sailesh Bissessur

Sailesh Bissessur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10680643
    Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.
    Type: Grant
    Filed: March 8, 2019
    Date of Patent: June 9, 2020
    Assignee: Intel Corporation
    Inventors: David K. Cassetti, Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar, Pradnyesh S. Gudadhe, Naveen Lakkakula, Brian Will, Atul Kwatra
  • Patent number: 10606841
    Abstract: Technologies for data compression include a computing device having multiple search agents. Each search agent searches a history of an input stream in parallel for a match to the input stream starting at a position based on an index of the search agent. Each search agent generates in parallel a weight value associated with the corresponding match. The weight value is indicative of a length associated with the match and an encoded length associated with the match. The encoded length is indicative of a number of bits to encode the match. The computing device selects a match based on the weight values. The computing device may output a token for the selected match and encode the token using a Huffman coding. Each search agent may be embodied as a hardware component or a software component such as a thread or process. Other embodiments are described and claimed.
    Type: Grant
    Filed: February 22, 2017
    Date of Patent: March 31, 2020
    Assignee: Intel Corporation
    Inventors: Pradnyesh S. Gudadhe, Lokpraveen B. Mosur, Sailesh Bissessur
  • Publication number: 20190273507
    Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.
    Type: Application
    Filed: March 8, 2019
    Publication date: September 5, 2019
    Inventors: David K. CASSETTI, Stephen T. PALERMO, Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL, Atul KWATRA
  • Publication number: 20190207624
    Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.
    Type: Application
    Filed: March 8, 2019
    Publication date: July 4, 2019
    Inventors: David K. CASSETTI, Stephen T. PALERMO, Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL, Atul KWATRA
  • Publication number: 20190123763
    Abstract: A compression engine includes sets of independent search engines. The sets of independent search engines concurrently perform searches for a longest match in a stream of uncompressed data. The searches are distributed amongst the sets of independent search engines on byte boundaries to load balance the use of the search engines.
    Type: Application
    Filed: December 20, 2018
    Publication date: April 25, 2019
    Inventors: Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, David K. CASSETTI, Stephen T. PALERMO, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL
  • Publication number: 20180239801
    Abstract: Technologies for data compression include a computing device having multiple search agents. Each search agent searches a history of an input stream in parallel for a match to the input stream starting at a position based on an index of the search agent. Each search agent generates in parallel a weight value associated with the corresponding match. The weight value is indicative of a length associated with the match and an encoded length associated with the match. The encoded length is indicative of a number of bits to encode the match. The computing device selects a match based on the weight values. The computing device may output a token for the selected match and encode the token using a Huffman coding. Each search agent may be embodied as a hardware component or a software component such as a thread or process. Other embodiments are described and claimed.
    Type: Application
    Filed: February 22, 2017
    Publication date: August 23, 2018
    Inventors: Pradnyesh S. Gudadhe, Lokpraveen B. Mosur, Sailesh Bissessur
  • Patent number: 9697899
    Abstract: Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: July 4, 2017
    Assignee: Intel Corporation
    Inventors: Lokpraveen B. Mosur, Sailesh Bissessur, Pradnyesh S. Gudadhe, Quinn W. Merrell
  • Publication number: 20170178729
    Abstract: Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: Lokpraveen B. MOSUR, Sailesh BISSESSUR, Pradnyesh S. GUDADHE, Quinn W. MERRELL
  • Patent number: 8766827
    Abstract: Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.
    Type: Grant
    Filed: March 29, 2013
    Date of Patent: July 1, 2014
    Assignee: Intel Corporation
    Inventors: Andrew Milne, Sailesh Bissessur, Quinn W. Merrell, Lokpraveen B. Mosur
  • Patent number: 8373583
    Abstract: An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.
    Type: Grant
    Filed: April 12, 2011
    Date of Patent: February 12, 2013
    Assignee: Intel Corporation
    Inventors: Lokpraveen B. Mosur, Sailesh Bissessur, Quinn W. Merrell, Prashant Paliwal, Andrew Milne
  • Publication number: 20120262312
    Abstract: An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.
    Type: Application
    Filed: April 12, 2011
    Publication date: October 18, 2012
    Inventors: Lokpraveen B. Mosur, Sailesh Bissessur, Quinn W. Merrell, Prashant Paliwal, Andrew Milne
  • Patent number: 7464199
    Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: December 9, 2008
    Assignee: Intel Corporation
    Inventors: Sailesh Bissessur, Richard P. Mackey, Mark A. Schmisseur, David R. Smith
  • Publication number: 20070079032
    Abstract: An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventors: Sailesh Bissessur, Joseph Murray, Brian Skerry, Robert Sheffield, Richard Beckett, Gregory Tse
  • Publication number: 20070073955
    Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.
    Type: Application
    Filed: September 29, 2005
    Publication date: March 29, 2007
    Inventors: Joseph Murray, Sailesh Bissessur, Shailendra Jha, Victor Lau, Bruno DiPlacido, Nai-Chih Chang, Suresh Chemudupati
  • Patent number: 7130933
    Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: October 31, 2006
    Assignee: Intel Corporation
    Inventors: Sailesh Bissessur, Richard P. Mackey, Mark A. Schmisseur, David R. Smith
  • Publication number: 20060168359
    Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.
    Type: Application
    Filed: April 7, 2006
    Publication date: July 27, 2006
    Inventors: Sailesh Bissessur, Richard Mackey, Mark Schmisseur, David Smith
  • Patent number: 7000146
    Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.
    Type: Grant
    Filed: May 31, 2001
    Date of Patent: February 14, 2006
    Assignee: Intel Corporation
    Inventors: Richard P. Mackey, Richard P. Luckett, James D. Warren, Sailesh Bissessur
  • Patent number: 6931457
    Abstract: Provided are a method, system and article of manufacture for controlling one or more I/O devices coupled to a local bus. A local bus function is associated with the one or more I/O devices. A register corresponding to the local bus function is configured as a memory address. The one or more I/O devices are controlled via the configured register.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: August 16, 2005
    Assignee: Intel Corporation
    Inventors: Sailesh Bissessur, David R. Smith
  • Patent number: 6820140
    Abstract: Provided are a method, system, and program for receiving a read request that is one of a plurality of read requests directed toward sequential data and determining whether at least one previous read request for sequential data preceding the data requested by the received read request was not processed. Data is returned to the received read request in response to returning data to the at least one previous read request.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: November 16, 2004
    Assignee: Intel Corporation
    Inventors: Sailesh Bissessur, Mark A. Schmisseur, David R. Smith
  • Patent number: 6807600
    Abstract: Provided are a method, system, and program for a local bus system. A memory address space in configured to control an I/O device. The memory address space is associated with a port coupled to the local bus system.
    Type: Grant
    Filed: July 24, 2002
    Date of Patent: October 19, 2004
    Assignee: Intel Corporation
    Inventors: Sailesh Bissessur, David R. Smith