Patents by Inventor Sailesh Bissessur
Sailesh Bissessur has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11431351Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.Type: GrantFiled: March 8, 2019Date of Patent: August 30, 2022Assignee: Intel CorporationInventors: David K. Cassetti, Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar, Pradnyesh S. Gudadhe, Naveen Lakkakula, Brian Will, Atul Kwatra
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Publication number: 20220103530Abstract: Examples described herein relate to a network interface device that includes circuitry, configured to perform encryption of data, generate one or more packets from the encrypted data, cause transmission of the one or more packets with the encrypted data, manage reliability of transport of the transmitted one or more packets with the encrypted data, and share protocol state information between a host system and the network interface device using connectivity based on user space accessible queues.Type: ApplicationFiled: December 7, 2021Publication date: March 31, 2022Inventors: Daniel DALY, Anjali Singhai JAIN, Yadong LI, Stephen DOYLE, Naru Dames SUNDAR, Chih-Jen CHANG, Sailesh BISSESSUR, Andrew CUNNINGHAM, Edwin VERPLANKE, Patrick FLEMING
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Publication number: 20210135685Abstract: Examples described herein relate to an encoder circuitry to apply one of multiple lossless data compression schemes on input data. In some examples, to compress input data, the encoder circuitry is to utilize a search window size and number of searches based on an applied compression scheme. In some examples, content of a memory is reconfigured to store data corresponding to a search window size of the applied compression scheme. In some examples, an applicable hash function is configured based on the applied compression scheme. In some examples, a number of searches are made for a byte position. In some examples, the encoder circuitry includes a hash table look-up and a bank decoder. In some examples, the hash table look-up is to generate a hash index to identify an address of an entry in the search window. In some examples, the bank decoder is to select a bank based on the hash index.Type: ApplicationFiled: December 11, 2020Publication date: May 6, 2021Inventors: Smita KUMAR, Sailesh BISSESSUR, David K. CASSETTI, Stephen T. PALERMO
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Patent number: 10680643Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.Type: GrantFiled: March 8, 2019Date of Patent: June 9, 2020Assignee: Intel CorporationInventors: David K. Cassetti, Stephen T. Palermo, Sailesh Bissessur, Patrick Fleming, Lokpraveen Mosur, Smita Kumar, Pradnyesh S. Gudadhe, Naveen Lakkakula, Brian Will, Atul Kwatra
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Patent number: 10606841Abstract: Technologies for data compression include a computing device having multiple search agents. Each search agent searches a history of an input stream in parallel for a match to the input stream starting at a position based on an index of the search agent. Each search agent generates in parallel a weight value associated with the corresponding match. The weight value is indicative of a length associated with the match and an encoded length associated with the match. The encoded length is indicative of a number of bits to encode the match. The computing device selects a match based on the weight values. The computing device may output a token for the selected match and encode the token using a Huffman coding. Each search agent may be embodied as a hardware component or a software component such as a thread or process. Other embodiments are described and claimed.Type: GrantFiled: February 22, 2017Date of Patent: March 31, 2020Assignee: Intel CorporationInventors: Pradnyesh S. Gudadhe, Lokpraveen B. Mosur, Sailesh Bissessur
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Publication number: 20190273507Abstract: In connection with compression of an input stream, multiple portions of the input stream are searched against previously received portions of the input stream to find any matches of character strings in the previously received portions of the input stream. In some cases, matches of longer character strings, as opposed to shorter character strings, can be selected for inclusion in an encoded stream that is to be compressed. Delayed selection can occur whereby among multiple matches, a match that is longer can be selected for inclusion in the encoded stream and non-selected a character string match is reverted to a literal. A search engine that is searching an input stream to identify a repeat pattern of characters can cease to search for characters that were included in the selected character string match.Type: ApplicationFiled: March 8, 2019Publication date: September 5, 2019Inventors: David K. CASSETTI, Stephen T. PALERMO, Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL, Atul KWATRA
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Publication number: 20190207624Abstract: A compression scheme can be selected for an input data stream based on characteristics of the input data stream. For example, when the input data stream is searched for pattern matches, input stream characteristics used to select a compression scheme can include one or more of: type and size of an input stream, a length of a pattern, a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, a gap between two pattern matches (including different or same patterns), standard deviation of a length of a pattern, standard deviation of a distance from a start of where the pattern is to be inserted to the beginning of where the pattern occurred previously, or standard deviation of a gap between two pattern matches. Criteria can be established whereby one or more characteristics are used to select a particular encoding scheme.Type: ApplicationFiled: March 8, 2019Publication date: July 4, 2019Inventors: David K. CASSETTI, Stephen T. PALERMO, Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL, Atul KWATRA
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Publication number: 20190123763Abstract: A compression engine includes sets of independent search engines. The sets of independent search engines concurrently perform searches for a longest match in a stream of uncompressed data. The searches are distributed amongst the sets of independent search engines on byte boundaries to load balance the use of the search engines.Type: ApplicationFiled: December 20, 2018Publication date: April 25, 2019Inventors: Sailesh BISSESSUR, Patrick FLEMING, Lokpraveen MOSUR, David K. CASSETTI, Stephen T. PALERMO, Smita KUMAR, Pradnyesh S. GUDADHE, Naveen LAKKAKULA, Brian WILL
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Publication number: 20180239801Abstract: Technologies for data compression include a computing device having multiple search agents. Each search agent searches a history of an input stream in parallel for a match to the input stream starting at a position based on an index of the search agent. Each search agent generates in parallel a weight value associated with the corresponding match. The weight value is indicative of a length associated with the match and an encoded length associated with the match. The encoded length is indicative of a number of bits to encode the match. The computing device selects a match based on the weight values. The computing device may output a token for the selected match and encode the token using a Huffman coding. Each search agent may be embodied as a hardware component or a software component such as a thread or process. Other embodiments are described and claimed.Type: ApplicationFiled: February 22, 2017Publication date: August 23, 2018Inventors: Pradnyesh S. Gudadhe, Lokpraveen B. Mosur, Sailesh Bissessur
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Patent number: 9697899Abstract: Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.Type: GrantFiled: December 21, 2015Date of Patent: July 4, 2017Assignee: Intel CorporationInventors: Lokpraveen B. Mosur, Sailesh Bissessur, Pradnyesh S. Gudadhe, Quinn W. Merrell
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Publication number: 20170178729Abstract: Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.Type: ApplicationFiled: December 21, 2015Publication date: June 22, 2017Inventors: Lokpraveen B. MOSUR, Sailesh BISSESSUR, Pradnyesh S. GUDADHE, Quinn W. MERRELL
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Patent number: 8766827Abstract: Parallel compression is performed on an input data stream by processing circuitry. The processing circuitry includes hashing circuitry, match engines, pipeline circuitry and a match selector. The hashing circuitry identifies multiple locations in one or more history buffers for searching for a target data in the input data stream. The match engines perform multiple searches in parallel for the target data in the one or more history buffers. The pipeline circuitry performs pipelined searches for multiple sequential target data in the input data stream in consecutive clock cycles. Then the match selector selects a result from the multiple searches and pipelined searches to compress the input data stream.Type: GrantFiled: March 29, 2013Date of Patent: July 1, 2014Assignee: Intel CorporationInventors: Andrew Milne, Sailesh Bissessur, Quinn W. Merrell, Lokpraveen B. Mosur
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Patent number: 8373583Abstract: An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.Type: GrantFiled: April 12, 2011Date of Patent: February 12, 2013Assignee: Intel CorporationInventors: Lokpraveen B. Mosur, Sailesh Bissessur, Quinn W. Merrell, Prashant Paliwal, Andrew Milne
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Publication number: 20120262312Abstract: An embodiment may include first circuitry and second circuitry. The first circuitry may compress, at least in part, based at least in part upon a first set of statistics, input to produce first output exhibiting a first compression ratio. If the first compression ratio is less than a desired compression ratio, the second circuitry may compress, at least in part, based at least in part upon a second set of statistics, the first output to produce second output. The first set of statistics may be based, at least in part, after an initial compression, upon other data that has been previously compressed and is associated, at least in part, with the input. The second set of statistics may be based at least in part upon the input. Many alternatives, variations, and modifications are possible.Type: ApplicationFiled: April 12, 2011Publication date: October 18, 2012Inventors: Lokpraveen B. Mosur, Sailesh Bissessur, Quinn W. Merrell, Prashant Paliwal, Andrew Milne
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Patent number: 7464199Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.Type: GrantFiled: April 7, 2006Date of Patent: December 9, 2008Assignee: Intel CorporationInventors: Sailesh Bissessur, Richard P. Mackey, Mark A. Schmisseur, David R. Smith
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Publication number: 20070079032Abstract: An apparatus may include a Serial General Purpose Input Output (SGPIO) initiator device. The SGPIO initiator device may have terminals to receive parallel input signals. The device may also have parallel-to-serial conversion logic to convert the parallel input signals to a serial stream. The device may further have signal ordering logic. The signal ordering logic may be in communication with the terminals and may be in communication with the parallel-to-serial conversion logic. The signal ordering logic may determine an order in which the parallel input signals are provided in the serial stream. Methods of ordering signals within an SGPIO initiator device and systems having SGPIO initiator devices are also disclosed.Type: ApplicationFiled: September 30, 2005Publication date: April 5, 2007Inventors: Sailesh Bissessur, Joseph Murray, Brian Skerry, Robert Sheffield, Richard Beckett, Gregory Tse
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Publication number: 20070073955Abstract: A multi-function peripheral component interconnect (PCI) device is disclosed. The device includes a first configuration data structure associated with a first PCI function, a second configuration data structure associated with a second PCI function and a PCI bridge, coupled the first and second configuration data structures. The PCI bridge processes transactions on behalf of the first and second functions.Type: ApplicationFiled: September 29, 2005Publication date: March 29, 2007Inventors: Joseph Murray, Sailesh Bissessur, Shailendra Jha, Victor Lau, Bruno DiPlacido, Nai-Chih Chang, Suresh Chemudupati
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Patent number: 7130933Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.Type: GrantFiled: July 24, 2002Date of Patent: October 31, 2006Assignee: Intel CorporationInventors: Sailesh Bissessur, Richard P. Mackey, Mark A. Schmisseur, David R. Smith
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Publication number: 20060168359Abstract: Provided are a method, system, and program for handling Input/Output (I/O) requests. A bus enables communication with an initiator, target device and device controller, wherein the device controller accesses the target device to execute I/O commands directed to the target device. An I/O request command is received to access the target device. The initiator is configured to transmit at least one data request on the bus to one memory address in a predefined address window of the device controller. The device controller is enabled to claim the data request to the memory address in the predefined address window from the initiator on the bus to execute the data request against the target device.Type: ApplicationFiled: April 7, 2006Publication date: July 27, 2006Inventors: Sailesh Bissessur, Richard Mackey, Mark Schmisseur, David Smith
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Patent number: 7000146Abstract: A memory system provides one or more control signals for configuring and controlling a memory sub-system during a power failure or system reset. A power delay circuit and a power fail controller cooperate to quickly place the memory system in a retention state in the event a power failure event is detected. The power delay circuit detects either a reset signal or power failure to initiate the memory retention state. The power delay circuit and power fail controller ensure the memory system is initialized prior to entering the retention state.Type: GrantFiled: May 31, 2001Date of Patent: February 14, 2006Assignee: Intel CorporationInventors: Richard P. Mackey, Richard P. Luckett, James D. Warren, Sailesh Bissessur