Patents by Inventor Sailesh Mansinh Merchant

Sailesh Mansinh Merchant has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7777333
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Grant
    Filed: February 24, 2006
    Date of Patent: August 17, 2010
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Patent number: 7678639
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: December 22, 2008
    Date of Patent: March 16, 2010
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 7566964
    Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: July 28, 2009
    Assignee: Agere Systems Inc.
    Inventors: Seung H. Kang, Roland P. Krebs, Kurt George Steiner, Michael C. Ayukawa, Sailesh Mansinh Merchant
  • Patent number: 7541238
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: May 1, 2006
    Date of Patent: June 2, 2009
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Publication number: 20090100668
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Application
    Filed: December 22, 2008
    Publication date: April 23, 2009
    Applicant: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Publication number: 20090072393
    Abstract: A solder bump structure and an under bump metallurgical structure. An upper surface of a semiconductor substrate comprises a first conductive pad (200) disposed thereon. A passivation layer (202) overlies the upper surface. A second conductive pad (212) is disposed in an opening (204) in the passivation layer and in contact with the first conductive pad. The under bump metallurgical structure (300) encapsulates the second conductive pad, covering an upper surface and sidewalls surfaces of the second conductive pad, protecting both the first and the second conductive pads from environmental and processing effects. According to the present invention, the conventional second passivation layer is not required. Methods for forming the various structures are also presented.
    Type: Application
    Filed: February 24, 2006
    Publication date: March 19, 2009
    Applicant: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Donald Stephen Bitting, Daniel Patrick Chesire, Taeho Kook, Sailesh Mansinh Merchant
  • Patent number: 7328830
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Grant
    Filed: December 19, 2003
    Date of Patent: February 12, 2008
    Assignee: Agere Systems Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
  • Patent number: 7301107
    Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
    Type: Grant
    Filed: October 27, 2003
    Date of Patent: November 27, 2007
    Assignee: Agere Systems, Inc.
    Inventors: Subramanian Karthikeyan, Sailesh Mansinh Merchant
  • Patent number: 7071563
    Abstract: An interconnect structure of a semiconductor device includes a tungsten plug (14) deposited in a via or contact window (11). A barrier layer (15) separates the tungsten plug (14) from the surface of a dielectric material (16) within which the contact window or via (11) is formed. The barrier layer (15) is a composite of at least two films. The first film formed on the surface of the dielectric material (16) within the via (11) is a tungsten silicide film (12). The second film is a tungsten film (13) formed on the tungsten silicide film (12). A tungsten plug (14) is formed on the tungsten film (13) to complete interconnect structure. The barrier layer (15) is deposited using a sputtering technique performed in a deposition chamber. The chamber includes tungsten silicide target (19) from which the tungsten silicide film (12) is deposited, and a tungsten coil (20) from which the tungsten film (20) is deposited.
    Type: Grant
    Filed: September 28, 2001
    Date of Patent: July 4, 2006
    Assignee: Agere Systems, Inc.
    Inventors: Siddhartha Bhowmik, Sailesh Mansinh Merchant, Darrell L. Simpson
  • Patent number: 7068139
    Abstract: An inductor formed within an integrated circuit and a method for forming the inductor. The inductor comprises an underlying layer of aluminum formed in a first metallization layer and patterned and etched into the desired shape. In one embodiment the aluminum line comprises a spiral shape. According to a damascene process, a conductive runner, preferably of copper, is formed in a dielectric layer overlying the aluminum line and in electrical contact therewith. The aluminum line and the conductive runner cooperate to form the inductor. In another embodiment the aluminum line and the conductive runner are formed in a vertically spaced-apart orientation, with tungsten plugs or conductive vias formed to provide electrical connection therebetween. A method for forming the inductor comprises forming an aluminum conductive line and forming a conductive runner over the conductive line.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 27, 2006
    Assignee: Agere Systems Inc.
    Inventors: Edward Belden Harris, Sailesh Mansinh Merchant, Kurt George Steiner, Susan Clay Vitkavage
  • Patent number: 6960836
    Abstract: Disclosed herein is a reinforcing system and method for reinforcing a contact pad of an integrated circuit. Specifically exemplified is a system and method that comprises a reinforcing structure interposed between a top contact pad layer and an underlying metal layer.
    Type: Grant
    Filed: September 30, 2003
    Date of Patent: November 1, 2005
    Assignee: Agere Systems, Inc.
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant, John William Osenbach, Kurt George Steiner
  • Patent number: 6869873
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Grant
    Filed: June 30, 2003
    Date of Patent: March 22, 2005
    Assignee: Agere Systems Inc.
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Publication number: 20040201101
    Abstract: An integrated circuit device structure and a process for fabricating the structure wherein the power bus interconnect structure is formed in the aluminum pad or contact layer. An interconnect structure for interconnecting underlying levels of interconnect can also be formed in the aluminum pad layer.
    Type: Application
    Filed: September 30, 2003
    Publication date: October 14, 2004
    Inventors: Seung H. Kang, Roland P. Krebs, Kurt George Steiner, Michael C. Ayukawa, Sailesh Mansinh Merchant
  • Publication number: 20040182915
    Abstract: An integrated circuit structure and a method for fabricating the structure. The method comprises forming a copper bond pad for attaching the integrated circuit to a package. Copper oxide is removed from the pad by reduction in a hydrogen ion atmosphere. For attaching the integrated circuit to a bump-bonding package an under-bump metallization layer is formed over the reduced copper pad and a solder bump formed thereover. The process can also be employed in a wire bonding process by forming an aluminum layer overlying the cleaned copper pad. The structure of the present invention comprises a copper pad formed in a substrate. A passivation layer defining an opening therein overlies the copper pad. A under-bump metallization layer is disposed in the opening and a solder bump overlies the metallization layer. Alternatively, the structure further comprises an aluminum pad disposed overlying the reduced copper pad.
    Type: Application
    Filed: December 19, 2003
    Publication date: September 23, 2004
    Inventors: Mark Adam Bachman, Daniel Patrick Chesire, Sailesh Mansinh Merchant
  • Patent number: 6790757
    Abstract: The present invention uses wire bonding technology to bond interconnect materials that oxidize easily by using a wire with stable oxidation qualities. A passivation layer is formed on the semiconductor substrate to encapsulate the bonding pad made from the interconnect material such that the wire bonds with the passivation layer itself, not with the interconnect material. The passivation layer is selected to be a material that is metallurgically stable when bonded to the interconnect material. Since the wire is stable compared with the interconnect material, i.e., it does not readily corrode, a reliable mechanical and electrical connection is provided between the semiconductor device (interconnect material) and the wire, with the passivation layer disposed therebetween.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: September 14, 2004
    Assignee: Agere Systems Inc.
    Inventors: Sailesh Chittipeddi, Sailesh Mansinh Merchant
  • Publication number: 20040106279
    Abstract: A system and method for eliminating interconnect extrusions in vias that are formed during ionized metal plasma processing. By eliminating interconnect extrusions in vias, reliability failures and yield loss are decreased. The extrusions of interconnect metallization occur while wafers are subject to elevated temperatures that cause the internal stresses in the interconnect metallization to transit from a substantially tensile mode to a substantially compressive mode. By controlling the interconnect temperature to be below the temperature at which the interconnect transits from a tensile to a compressive mode, interconnect extrusions in vias are eliminated. The interconnect temperature is controlled by using an actively cooled pedestal in combination with a low temperature IMP deposition process. In addition, the IMP processing time may also be decreased to limit heating of the interconnect.
    Type: Application
    Filed: November 12, 2003
    Publication date: June 3, 2004
    Inventors: Steven Mark Anderson, Siddhartha Bhowmik, Joseph William Buckfeller, Sailesh Mansinh Merchant, Frank Minardi
  • Publication number: 20040097075
    Abstract: A silane passivation process, carried out in-situ together with the formation of a subsequent dielectric film, converts the exposed Cu surfaces of a Cu interconnect structure, to copper silicide. The copper silicide suppresses Cu diffusion and electromigration and serves as a barrier material in regions where contact to further conductive material is made. An entire copper surface of a copper interconnect structure may be silicided or a local portion of the surface silicided after an opening is formed in an overlying dielectric to expose a portion of the copper surface.
    Type: Application
    Filed: June 30, 2003
    Publication date: May 20, 2004
    Inventors: Robert Wayne Bradshaw, Daniele Gilkes, Sailesh Mansinh Merchant, Deepak A. Ramappa, Kurt George Steiner
  • Publication number: 20040084761
    Abstract: An interconnect structure of a semiconductor device designed for reduced intralevel and interlevel capacitance, and includes a lower metal layer and an upper metal layer and an insulating layer interposed between metal layers. Each of the lower metal layer and upper metal layer include a plurality of conductive lines spaced apart and extending within a low-k dielectric material. A plurality of metal-filled vias interconnects the conductive lines of the lower metal layer to the conductive lines of the upper metal layer. The insulating layer comprises also comprises a low-k dielectric material disposed between the adjacent metal-filled vias. Openings, having been etched in the low-k dielectric material between the conductive lines of the upper and lower metal layers, and the metal-filled vias, an ultra-low k material is deposited within the openings. The integration of the ultra-low k and low-d dielectric materials reduces the overall capacitance of the structure to enhance performance.
    Type: Application
    Filed: October 27, 2003
    Publication date: May 6, 2004
    Inventors: Subramanian Karthikeyan, Sailesh Mansinh Merchant
  • Patent number: 6730601
    Abstract: A method of fabricating a metal-oxide-metal capacitor in a microelectronic device is provided. First, a recess is formed in a surface of a dielectric layer deposited over a microelectronic substrate. A first barrier layer is then deposited over the dielectric layer such that the first barrier layer conforms to the recess. A first conductive element is then deposited over the first barrier layer so as to at least fill the recess. A second barrier layer is further deposited over the first conductive element such that the first barrier layer and the second barrier layer cooperate to encapsulate the first conductive element. The first conductive element thus comprises a first plate of the capacitor. A capacitor dielectric layer is then deposited over the second barrier layer, followed by the deposition of a second conductive element over the capacitor dielectric layer. The second conductive element thus comprises a second plate of the capacitor.
    Type: Grant
    Filed: February 21, 2002
    Date of Patent: May 4, 2004
    Assignee: Agere Systems, Inc.
    Inventors: Edward Belden Harris, Yifeng Winston Yan, Sailesh Mansinh Merchant
  • Patent number: 6730600
    Abstract: A method for dry etching a material deposited on semiconductor device is performed by chemically reacting the material with an etchant gas. The etching process is conducted in a reaction chamber at a predetermined temperature and predetermined pressure within the reaction chamber and without the need of generating a plasma within the chamber or applying an electrical bias to the semiconductor device. A sufficient amount of gas is introduced into the reaction chamber to selectively remove the material from the semiconductor device.
    Type: Grant
    Filed: September 27, 2002
    Date of Patent: May 4, 2004
    Assignee: Agere Systems, Inc.
    Inventors: Nace Layadi, Simon John Molloy, Sailesh Mansinh Merchant, Isik C. Kizilyalli