Abstract: The present disclosure relates to a disaggregated computing architecture comprising: a first compute node (302) comprising an interconnect interface (310); an accelerator node (304) comprising a physical device (402); and an interconnection network (308) linking the first compute node (302) and the accelerator node (304), wherein: the first compute node (302) executes a host operating system (410) and instantiates a first virtual machine (VM) executing a guest device driver (406) for driving the physical device; one or more input registers of the physical device are accessible via a first uniform physical address range (upa_a_devctl) of the interconnection network (308); and the interconnect interface (310) of the first compute node (302) is configured to map a host physical address range (hpa_c_devctl) of the host operating system (410) to the first uniform physical address range (upa_a_devctl).

Abstract: The present disclosure relates to a disaggregated computing architecture comprising: a first compute node (302) comprising an interconnect interface (310); an accelerator node (304) comprising a physical device (402); and an interconnection network (308) linking the first compute node (302) and the accelerator node (304), wherein: the first compute node (302) executes a host operating system (410) and instantiates a first virtual machine (VM) executing a guest device driver (406) for driving the physical device; one or more input registers of the physical device are accessible via a first uniform physical address range (upa_a_devctl) of the interconnection network (308); and the interconnect interface (310) of the first compute node (302) is configured to map a host physical address range (hpa_c_devctl) of the host operating system (410) to the first uniform physical address range (upaa_devctl).

Abstract: The invention concerns a processing system comprising: a compute node (20) having one or more processors and one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support a plurality of virtual machines (VM1); a reconfigurable circuit (301) comprising a dynamically reconfigurable portion (302) comprising one or more partitions (304) that are reconfigurable during runtime and implement at least one hardware accelerator (ACC #1 to #N) assigned to at least one of the plurality of virtual machines (VM); and a virtualization manager (306) providing an interface between the at least one hardware accelerator (ACC #1 to #N) and the compute node (202) and comprising a circuit (406) adapted to translate, for the at least one hardware accelerator, virtual memory addresses into corresponding physical memory addresses to permit communication between the one or more hardware accelerators and the plurality of virtual machines.

Abstract: The invention concerns a multi-core processing system comprising: a first input/output interface (312) configured to transmit data over a first network (313) based on a first network protocol; a second input/output interface (314) configured to transmit data over a second network (315) based on a second network protocol; a plurality of processing cores; and one or more memory devices storing software enabling virtual processing resources of the plurality of processing cores and virtual memory to be assigned to support: a first compartment (303) implementing one or more first virtual machines; a second compartment (304) implementing one or more second virtual machines; and a programmable virtual switch (302) configured to provide an interface between the first and second virtual machines and the first and second input/output interfaces (312, 314).

Abstract: The invention concerns a compute node comprising: one or more processors; one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support:—a virtual machines compartment (402) in which a plurality of virtual machines (VM) is enabled by a hypervisor; and—a services compartment (404) comprising an operating system (OS) enabling one or more of real time capabilities, security functionality, and hardware accelerators, wherein the services compartment further comprises a virtual machines service manager (412) adapted to manage service requests received from the virtual machines; and a hardware partition (418) providing access control between the virtual machines (408) and the virtual machines services compartment (404).

Abstract: The invention concerns a multi-core processing system comprising: a first input/output interface (312) configured to transmit data over a first network (313) based on a first network protocol; a second input/output interface (314) configured to transmit data over a second network (315) based on a second network protocol; a plurality of processing cores; and one or more memory devices storing software enabling virtual processing resources of the plurality of processing cores and virtual memory to be assigned to support: a first compartment (303) implementing one or more first virtual machines; a second compartment (304) implementing one or more second virtual machines; and a programmable virtual switch (302) configured to provide an interface between the first and second virtual machines and the first and second input/output interfaces (312, 314).

Abstract: The invention concerns a processing system comprising: a compute node (20) having one or more processors and one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support a plurality of virtual machines (VM1); a reconfigurable circuit (301) comprising a dynamically reconfigurable portion (302) comprising one or more partitions (304) that are reconfigurable during runtime and implement at least one hardware accelerator (ACC #1 to #N) assigned to at least one of the plurality of virtual machines (VM); and a virtualization manager (306) providing an interface between the at least one hardware accelerator (ACC #1 to #N) and the compute node (202) and comprising a circuit (406) adapted to translate, for the at least one hardware accelerator, virtual memory addresses into corresponding physical memory addresses to permit communication between the one or more hardware accelerators and the plurality of virtual machines.

Abstract: The invention concerns a compute node comprising: one or more processors; one or more memory devices storing software enabling virtual computing resources and virtual memory to be assigned to support:—a virtual machines compartment (402) in which a plurality of virtual machines (VM) is enabled by a hypervisor; and—a services compartment (404) comprising an operating system (OS) enabling one or more of real time capabilities, security functionality, and hardware accelerators, wherein the services compartment further comprises a virtual machines service manager (412) adapted to manage service requests received from the virtual machines; and a hardware partition (418) providing access control between the virtual machines (408) and the virtual machines services compartment (404).