Patents by Inventor Salvatore Levantino
Salvatore Levantino has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240128871Abstract: A boost DC-DC converter includes a switching network, coupled to an inductor, controlled by a PWM driving signal. A control loop receives a voltage output and provides the PWM driving signal. The control loop generates an error signal as a function of a difference between voltage output voltage and a reference, with the PWM driving signal generated based on the error signal. A low pass filter circuit within the control loop receives the PWM driving signal and provides at least one filtered signal. An adder node of the control loop receives the at least one filtered signal from the low pass filter circuit for addition to the at least one filtered signal. The PWM driving signal is generated as a function of a sum of the filtered signal and the error signal.Type: ApplicationFiled: October 3, 2023Publication date: April 18, 2024Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alessandro GASPARINI, Paolo MELILLO, Salvatore LEVANTINO, Massimo GHIONI
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Patent number: 11837953Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.Type: GrantFiled: July 20, 2022Date of Patent: December 5, 2023Assignee: STMicroelectronics S.r.l.Inventors: Alessandro Dago, Alessandro Gasparini, Osvaldo Enrico Zambetti, Salvatore Levantino, Massimo Antonio Ghioni
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Publication number: 20230336078Abstract: In a multi-level hybrid DC-DC converter with a flying capacitor, a feedback circuit includes a first oscillator and produces a first clock signal with a frequency dependent on an output voltage. A second oscillator produces a second clock signal having a frequency dependent on a reference voltage. A logic circuit switches, as a function of the first and second clock signals, connection of the flying capacitor between one state where the flying capacitor is connected between an input node and a switching node, and another state where the capacitor is connected between the switching node and a ground node. The duty cycle of the first/second clock signal varies so that when the flying capacitor voltage is lower than a target voltage a duration of the one state is increased, and when the flying capacitor voltage is higher than the target voltage a duration of the another state is increased.Type: ApplicationFiled: April 10, 2023Publication date: October 19, 2023Applicant: STMicroelectronics S.r.l.Inventors: Alessandro BERTOLINI, Alessandro GASPARINI, Paolo MELILLO, Salvatore LEVANTINO, Massimo GHIONI
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Publication number: 20230055825Abstract: A Single Input Dual Output converter includes a first switch coupling an input to a first inductor terminal, a second switch coupling a second inductor terminal to ground, a third switch coupling the second inductor terminal to a positive output, and a fourth switch coupling the first inductor terminal to a negative output. During time-shared control, the negative and positive outputs are independently served by conversion cycles. Each conversion cycle includes: a positive phase with a positive charge phase (closing only the first and second switches), followed by an additional phase (closing only the first and third switches for a given time duration), and followed by a positive discharge phase (closing only the third and fourth switches). Each conversion cycle further includes a negative phase with a negative charge phase (closing only the first and second switches) followed by a negative discharge phase (closing only the second and fourth switches).Type: ApplicationFiled: August 11, 2022Publication date: February 23, 2023Applicant: STMicroelectronics S.r.l.Inventors: Alessandro GASPARINI, Mauro LEONCINI, Claudio LUISE, Alberto CATTANI, Massimo GHIONI, Salvatore LEVANTINO
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Publication number: 20230034786Abstract: First and second circuit branches are coupled between an input node and ground. Each circuit branch includes a series coupling first-fourth transistors in a current flow path with an output node. A first capacitor is coupled between a first capacitor node and a second capacitor node intermediate the first transistor and the second transistor in the first circuit branch. A second capacitor is coupled between a third capacitor node and a fourth capacitor node intermediate the first transistor and the second transistor in the second circuit branch. An inter-branch circuit block between the first and second branches includes a first inter-branch transistor coupled between the first capacitor node in the first circuit branch and the fourth capacitor node in the second circuit branch and a second inter-branch transistor coupled between the third capacitor node in the second circuit branch and the second capacitor node in the first circuit branch.Type: ApplicationFiled: July 20, 2022Publication date: February 2, 2023Applicant: STMicroelectronics S.r.l.Inventors: Alessandro DAGO, Alessandro GASPARINI, Osvaldo Enrico ZAMBETTI, Salvatore LEVANTINO, Massimo Antonio GHIONI
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Patent number: 11454715Abstract: Systems, methods, and circuitries are provided for generating a frequency hopping radar signal. In one example, a radar signal modulator include a frequency offset generator, a phase locked loop, and a bandwidth compensation circuitry. The frequency offset generator is configured to generate a sequence of frequency offsets. The bandwidth compensation circuitry is configured to combine a modulation signal and the sequence of frequency offsets to generate a bandwidth compensated signal. The PLL is configured to receive the bandwidth compensated signal and generate a frequency hopping radar signal based on the bandwidth compensated signal.Type: GrantFiled: December 6, 2019Date of Patent: September 27, 2022Assignees: Infineon Technologies AG, POLITECNICO DI MILANOInventors: Dmytro Cherniak, Salvatore Levantino, Mario Mercandelli
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Patent number: 11418199Abstract: In accordance with an embodiment, a method of operating a phase locked loop (PLL), the method including: comparing a phase of a reference signal with a phase of a clock signal using a plurality of parallel matched phase detection circuits to provide a plurality of phase detection signals, where each of the plurality of the parallel matched phase detection circuits is configured to have a same phase difference to output characteristic; filtering a sum of the plurality of phase detection signals to form a filtered phase detection signal; and controlling a frequency of an oscillator using the filtered phase detection signal, where the oscillator is configured to provide the clock signal.Type: GrantFiled: May 21, 2021Date of Patent: August 16, 2022Assignees: INFINEON TECHNOLOGIES AG, POLITECNICO DI MILANOInventors: Dmytro Cherniak, Salvatore Levantino, Alessio Santiccioli
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Publication number: 20220216789Abstract: A time based boost DC-DC converter generates an output voltage using an inductor. A voltage error between the output voltage and a reference voltage is determined and processed in a) an integral control branch which converts the voltage error into an integral control current signal used to control a current controlled oscillator, and b) a proportional branch which converts the voltage error into a proportional control current signal used to control signal a delay line. Current flowing in the inductor is sensed, attenuated and used to apply adjustment to the integral and proportional control current signals. The output from the current controlled oscillator is passed through the delay line and phase detected in order to generate pulse width modulation (PWM) control signaling driving switch operation in the converter.Type: ApplicationFiled: January 5, 2022Publication date: July 7, 2022Applicant: STMicroelectronics S.r.l.Inventors: Alessandro GASPARINI, Alessandro BERTOLINI, Mauro LEONCINI, Massimo GHIONI, Salvatore LEVANTINO
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Patent number: 11233520Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.Type: GrantFiled: October 16, 2020Date of Patent: January 25, 2022Assignee: Infineon Technologies AGInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20210173070Abstract: Systems, methods, and circuitries are provided for generating a frequency hopping radar signal. In one example, a radar signal modulator include a frequency offset generator, a phase locked loop, and a bandwidth compensation circuitry. The frequency offset generator is configured to generate a sequence of frequency offsets. The bandwidth compensation circuitry is configured to combine a modulation signal and the sequence of frequency offsets to generate a bandwidth compensated signal. The PLL is configured to receive the bandwidth compensated signal and generate a frequency hopping radar signal based on the bandwidth compensated signal.Type: ApplicationFiled: December 6, 2019Publication date: June 10, 2021Inventors: Dmytro Cherniak, Salvatore Levantino, Mario Mercandelli
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Publication number: 20210036710Abstract: A phased-locked loop (PLL) circuit with an injection locked digital digitally controlled oscillator (ILD) that has an ILD control input element, an ILD injection input element and an ILD output element. The PLL circuit also includes an adaptive control unit (ACU), wherein the ACU is configured to receive an error signal and is configured to output an ILD control word. The ILD control input element is configured to receive the ILD control word, and the ILD control word may set a natural oscillation frequency of the ILD. The ILD is further configured to output a first output signal from the ILD output element, where the natural oscillation frequency may set a frequency of the first output signal.Type: ApplicationFiled: October 16, 2020Publication date: February 4, 2021Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 10826508Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: GrantFiled: November 13, 2018Date of Patent: November 3, 2020Assignee: Infineon Technologies AGInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20190081633Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: ApplicationFiled: November 13, 2018Publication date: March 14, 2019Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 10135452Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: GrantFiled: February 21, 2017Date of Patent: November 20, 2018Assignees: Infineon Technologies AG, Politecnico Di MilanoInventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Publication number: 20180241406Abstract: The disclosure is directed to a frequency synthesizer circuit including digitally controlled oscillator (DCO) and an injection locked digitally controlled oscillator (ILD). The ILD outputs a signal with a frequency that is some fraction of the frequency of the DCO output signal and locked in phase to the DCO output signal. The frequency synthesizer circuit drives the ILD with the same modulation input signal that drives the DCO, with the modulation input signal scaled to account for any mismatch between the gains of the DCO and ILD. Driving the ILD with the same, scaled modulation signal as the main DCO minimizes the frequency offset between the DCO output signal and the divided natural oscillation frequency of the ILD. Minimizing the frequency offset makes the lock of the ILD more robust and reduces jitter contribution from the ILD.Type: ApplicationFiled: February 21, 2017Publication date: August 23, 2018Inventors: Dmytro Cherniak, Salvatore Levantino, Marc Tiebout, Roberto Nonis
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Patent number: 8571161Abstract: It is described an electronic device for generating a fractional synthesized frequency. The device comprises a multi-phase controlled oscillator configured to generate, from a control signal, a plurality of signals phase-shifted each other and comprises a phase detector configured to receive a selected signal from the plurality of phase-shifted signals, to receive a reference signal and to measure a difference between a phase of the selected signal and a phase of the reference signal. The electronic device further comprises control means for estimating, from the measured phase difference, a phase error affecting the generation of at least one of the plurality of phase-shifted signals, and for generating a corrected measure of the phase difference taking into account the estimated phase error, the corrected measure being used to provide the control signal.Type: GrantFiled: February 3, 2010Date of Patent: October 29, 2013Assignee: Politechnico di MilanoInventors: Salvatore Levantino, Carlo Samori, Marco Zanuso
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Publication number: 20110286510Abstract: It is described an electronic device for generating a fractional synthesized frequency. The device comprises a multi-phase controlled oscillator configured to generate, from a control signal, a plurality of signals phase-shifted each other and comprises a phase detector configured to receive a selected signal from the plurality of phase-shifted signals, to receive a reference signal and to measure a difference between a phase of the selected signal and a phase of the reference signal. The electronic device further comprises control means for estimating, from the measured phase difference, a phase error affecting the generation of at least one of the plurality of phase-shifted signals, and for generating a corrected measure of the phase difference taking into account the estimated phase error, the corrected measure being used to provide the control signal.Type: ApplicationFiled: February 3, 2010Publication date: November 24, 2011Applicant: POLITECNICO DI MILANOInventors: Salvatore Levantino, Carlo Samori, Marco Zanuso
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Patent number: 6911870Abstract: A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.Type: GrantFiled: July 31, 2003Date of Patent: June 28, 2005Assignee: Agere Systems, Inc.Inventors: Sander L. Gierkink, Vito Boccuzzi, Robert C. Frye, Salvatore Levantino
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Publication number: 20040127172Abstract: The present invention provides a phase-error suppressor for use with a plurality of transistors having a common source coupled to a current generator that receives signals at a frequency. In one embodiment, the phase-error suppressor includes an inductor, coupled between the common source and the current generator, that resonates proportionally to the frequency with a first capacitance associated with the plurality of transistors. In one embodiment, the inductor resonates at about twice the frequency wherein input phase error is suppressed at output.Type: ApplicationFiled: July 28, 2003Publication date: July 1, 2004Applicant: Agere Systems Inc.Inventors: Sander L. Gierkink, Salvatore Levantino
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Publication number: 20040066241Abstract: A voltage controlled oscillator including a first oscillator circuit portion with at least one first inductor, and a second oscillator circuit portion with at least one second inductor, wherein the at least one first inductor and the at least one second inductor are electromagnetically coupled to each other.Type: ApplicationFiled: July 31, 2003Publication date: April 8, 2004Inventors: Sander L. Gierkink, Vito Boccuzzi, Robert C. Frye, Salvatore Levantino