Abstract: A multi-channel power shut-down circuit that includes a plurality of channel disabler circuits formed on a common substrate where each of the channel disabler circuits includes a first combinational logic and a second combinational logic having an input coupled to an output of the first combinational logic and having a channel disable output, and a channel overcurrent detector coupled to an input of the first combinational logic. A thermal warning detector is also formed on the common substrate and coupled to the inputs of the first combinational logic of the plurality of channel disabler circuits. A thermal shutdown detector formed on the common substrate and coupled to the inputs of the second combinational logic of the plurality of channel disabler circuits.

Abstract: A multi-channel power shut-down circuit that includes a plurality of channel disabler circuits formed on a common substrate where each of the channel disabler circuits includes a first combinational logic and a second combinational logic having an input coupled to an output of the first combinational logic and having a channel disable output, and a channel overcurrent detector coupled to an input of the first combinational logic. A thermal warning detector is also formed on the common substrate and coupled to the inputs of the first combinational logic of the plurality of channel disabler circuits. A thermal shutdown detector formed on the common substrate and coupled to the inputs of the second combinational logic of the plurality of channel disabler circuits.

Abstract: This invention relates to a circuit structure of the feedforward type with programmable zeroes, particularly for synthesizing time-continual filters. This structure comprises a pair of amplification cells interconnected at least one interconnection node and connected between a first signal input of a first cell and an output terminal of the second cell, each cell comprising a pair of transistors which have a conduction terminal in common and have the other conduction terminals coupled respectively to a first voltage reference through respective bias members. The structure further comprises a circuit leg connecting a node of the first cell to the output terminal and comprising a transistor which has a control terminal connected to the node of the first cell, a first conduction terminal connected to the output terminal, and a second conduction terminal coupled to a second voltage reference through a capacitor.

Abstract: A method of equalizing a read channel of a mass magnetic memory device comprises attenuating the low frequencies of the spectrum of the analog signal originating from an electromagnetic read transducer without boosting the high frequency harmonic components of the spectrum. The low frequencies of the spectrum of the analog input signal are attenuated with a low pass filter of an order in a range from 6 to 8 and a boost is implemented by introducing two real and opposed zeroes in the transfer function of the filter without altering the group delay.

Abstract: The method is for controlling a voice coil motor which drives a mechanical arm via a control circuit which sets the output nodes, to which the motor is connected, in a high impedance state for a certain time interval. The method and circuit detect the back electromotive force induced on the motor winding during the time interval, and deliver current pulses for driving the motor. The circuit compares the detected back electromotive force with a certain target value and regulates the amplitude of the driving current pulses as a function of the difference between the detected value of the back electromotive force and a voltage signal representing the desired speed of the arm, according to a pre-established function. A preferred embodiment includes such a function being a pre-established saturated linear characteristic with an offset value.

Abstract: The monitoring of multiple supply voltages of an integrated circuit is done using a single external capacitor connected to a pin of the integrated circuit. Part of the multiple supply voltages are externally generated and part are internally generated. The internally generated supply voltages may include different voltages with different signs. A logic signal indicating that all the supply voltages have reached pre-established values before enabling functioning of the integrated circuit is generated after an initial soft start phase of the turn-on process.

Abstract: A switching regulator having a switching element, a control loop for varying a duty cycle of the switching element according to a difference between a switching regulator output electric quantity and a target output electric quantity, and a digital soft start-up circuit for digitally controlling the duty cycle of the switching element, independently from said difference, in a start-up phase of the switching regulator operation.

Abstract: A programmable-gain multistage amplifier with broad bandwidth and reduced phase variations having a differential input stage biased by a first current source and to which a differential voltage signal is fed, the stage being connected to a pair of diodes in which the cathode terminals are connected to respective bipolar transistors, which are biased by a second current source and in which the collector terminals are connected to load resistors, the differential output of the amplifier being provided at the collector terminals of the bipolar transistors.

Abstract: A driver circuit includes a half-bridge output stage including two transistors with a common terminal for connection as the driver output to a coil of a DC motor. Two amplifiers drive the transistors in the push-pull operation and two capacitors are connected between the driver output and one input of a respective amplifier to form feedback loops for controlling the output slew-rate. Two current generators are selectively connected to an input of either of the amplifiers through respective pairs of switches. A commutation sequencer turns on and off the switches according to a commutation program. Comparators are connected to the drive output for detecting predetermined output voltage conditions and providing the commutation sequencer with signals for conditioning the commutation program as a function of the detected voltage conditions.

Abstract: Embodiments of the invention provide a transconductance control circuit, particularly for a continuous-time filter, comprising a transconductor across which a constant voltage is input. The transconductor is connected to a digital-to-analog converter (DAC) to set a reference current. A feedback loop is provided between an output of the transconductor and an input. In particular, the circuit further comprises a means for mirroring the reference current set by the DAC both to the feedback loop and to at least one cell of a cascade-connected filter.

Abstract: A device generates pulses of high-precision with programmable duration. The device includes first, second and third pulse generator circuits. The first pulse generator circuit receives at an input a pulse generation command signal, and provides at an output a first pulse for loading the contents of a register in a counter. The second pulse generator circuit is triggered by the first pulse provided by the first pulse generator circuit. The third pulse generator circuit is triggered by a second pulse provided by the second pulse generator circuit, and generates a third pulse to restart the second pulse generator circuit. The second pulse provided by the second pulse generator circuit forms a clock signal for the counter to produce a decrement in the counter. The output signal from the counter is the pulsed signal to be generated. The duration of the pulsed signal is determined by the content of the counter.

Abstract: A feedforward circuit structure with programmable zeros for synthesizing continuous-time filters, delay lines, and the like is described. The circuit comprises a first cell and a second cell which are cascade-connected. Each one of the first and second cells comprises first and second pairs of bipolar transistors. The emitter terminals of the first pair of transistors are connected to a first current source, and the emitter terminals of the second pair of transistors are connected to a second current source. A first high-impedance element is connected between the first and second pairs of transistors, and a second high-impedance element is connected at an output of the second pair of transistors. A fifth transistor is connected between the collector terminal of a first transistor of the first pair of transistors and the collector terminal of a second transistor of the second pair of transistors.

Abstract: An amplifier with programmable gain and input linearity at high frequency allows an increase in the gain without effecting input linearity and without significantly increasing current consumption. The amplifier includes an input stage which receives a voltage signal for performing a current conversion thereof with compression. An output stage is connected to the input stage and decompresses the signal provided by the input stage for producing gain amplification thereof. The amplifier further includes at least one current amplifier stage interposed between the input stage and the output stage. The at least one current amplifier includes at least one bipolar transistor series-connected to a load diode and to a current source. A reduction in the transconductance of the load diode is provided in the at least one amplifier stage to determine a programmable gain factor for the amplifier.

Abstract: An analog multiplier includes at least a differential output stage formed by a pair of emitter-coupled bipolar transistors. Each transistor of the pair of emitter-coupled bipolar transistors is driven by a predistortion stage having a reciprocal of a hyperbolic tangent transfer function that is attributable to the base currents of the bipolar transistors used in the predistortion stage. The error in the output signal produced by the analog multiplier is compensated by generating replicas of the base currents of the bipolar transistors of the differential output stage and forcing those replica currents on the output node of a respective predistortion stage. Various embodiments that consume different amounts of power are described.

Abstract: A fully integrated, phase locked loop (PLL) having improved jitter characteristics uses the same digital/analog converter (DAC) that is normally used to control the time constant of the low pass loop filter to control the value of a capacitance connected between the output of a voltage-to-current converting input stage of the voltage controlled oscillator and ground. The capacitance introduces a third pole in the loop's transfer function. In this way, the separation in the frequency domain between the zero and the third pole of the transfer function is kept constant; thus, the damping factor remains constant while the .omega..sub.0 of the PLL is varied.

Abstract: A threshold voltage generator for a field-effect transistor, being of a type adapted to compensate for variations of the threshold voltage from a nominal value, comprising a first amplifier having a first input connected to a current generator; a second amplifier connected ahead of a second input of the first amplifier and having an input connected to another current generator; and a third amplifier connected after the first amplifier and having an output adapted to produce the value of said threshold voltage.

Abstract: A variable gain amplifier which includes a first voltage-to-current amplifier having a fixed gain; a second voltage-to-current amplifier having a variable gain, functioning in parallel to said first amplifier; a gain control and stabilization variable current generator; and a current-to-voltage converter. Current output signals produced by said first and second amplifiers and by said variable current generator are summed and the resulting current signal is converted to a voltage signal by said converter.

Abstract: A fast capacitive-load driving circuit for driving output nodes on an integrated circuit. This circuit reduces noise interference caused by parasitic inductance by lowering the inductance voltage on the power supply lines during the switching process. This invention includes a voltage ramp, a voltage-to-current converter, and an output buffer having at least one pull-down transistor. A further embodiment includes an output buffer possessing a pull-down and a pull-up transistor.