Abstract: A scanning probe microscope having a probe attachment fixture, to which a probe assembly is removably attached during measurements, driven in an engagement direction, and a sample stage driven in scanning directions perpendicular to the engagement direction includes a buffer with a number of buffer stations within the sample stage. When the stage is driven so that one of the buffer stations is in alignment with the attachment fixture, and when the attachment fixture is driven in the engagement direction to be in proximity to the buffer station, the probe assembly is selectively transferred in either direction between the attachment fixture and the buffer station. In a preferred embodiment, probe assemblies are transferred on transfer pallets, and a stationary magazine is provided for storing these pallets, which are transferred in either direction between the magazine and the buffer.

Abstract: This invention is directed toward a loop compensator which dynamically changes the compensation break points as a function of duty cycle, input voltage and output load current to insure system loop stability. The system identifier of the dynamic loop compensator identifies the converter circuit topology to which it is connected and relays corresponding circuit identification signals to a digital controller. Based on the identification signals, the digital controller implements one of three compensation algorithms that dynamically changes the compensation break points and consequently insures closed loop stability. Based upon system condition signals and one of the three compensation algorithms, the digital controller changes the compensation break points by producing variable frequency clock signals which are input into a bank of capacitors in a switching capcitor error amplifier network.

Abstract: A PLL (phase-locked loop) circuit is used in apparatus for testing individual circuits in circuit devices. The PLL circuit operates at an input frequency provided by the output of an input oscillator when this oscillator is connected to one of the inputs of a phase comparator within the PLL circuit. When this connection is not made, the PLL circuit operates at a freerunning frequency, which is varied by connecting a circuit under test with a frequency controlling node present within a voltage-controlled oscillator in the PLL circuit. In a first mode of operation, the circuit under test is initially connected to the frequency controlling node, but the input oscillator is not connected to the phase comparator. When the input oscillator is so connected, the frequency of oscillations moves from a freerunning frequency associated with the circuit under test to the input frequency.

Abstract: A serial-to-parallel converter comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of serial-to-parallel converter cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be read when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the serial-to-parallel converter.

Abstract: A parallel-to-serial converter comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of parallel-to-serial converter cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be read when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the parallel-to-serial converter.

Abstract: An apparatus is disclosed for quickly testing individual wiring nets in a multi-layer device carrier. A central processing unit (CPU) controls a probe to sequentially engage contact pads on the carrier, each of which is electrically connected to a respective wiring net. The probe connects each wiring net to a network sensitive pulse generator circuit which generates a train of output pulses having a frequency dependent upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates the series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response.

Abstract: A network sensitive pulse generator circuit and a method of using the circuit to quickly detect faults in a net under test are described. The novel circuit generates pulses which depend upon the transient behavior of the net under test. The stimulation of the net and the sensing of the net's response operate responsively to a feedback signal, which is also a signature signal. By connecting the net under test to the novel circuit, the combination of the novel circuit and the net under test generates a series of output pulses. The number of pulses generated in a predetermined period of time forms the signature of the net under test. A preferred embodiment is described which uses differential amplifiers to stimulate the net and to sense the net's response. The differential amplifier which senses the net's response is connected to a circuit which produces the feedback/signature signal. The feedback/signal is then provide to the differential amplifiers to adjust their behavior.

Abstract: A memory controller generates control and address signal for accessing a non-volatile memory having a plurality of addressable cells. Each cell of the non-volatile memory includes a floating gate transistor (e.g., Q15) capable of storing charge (representing a binary 1 or 0) for extended, although not indefinite, periods of time. To refresh any charge that leaks off the floating gate, refresh circuitry (e.g., Q17-Q19) is provided to restore the charge on the gate to its original logical state. This refresh circuitry may be activated at "power-up." Each of the transistors in the memory are preferably thin film, amorphous silicon, "N" type transistors, including the floating gate transistor.

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A driver circuit has hysteresis. The driver circuit includes a comparator circuit having first and second inputs and an output. The driver circuit also includes a variable voltage divider circuit coupled between the second input and the output of said comparator. The voltage divider circuit provides a first voltage to the second input of the comparator when the output of the comparator is at a second voltage, and a third voltage to the second input of the comparator when the output of the comparator is at a fourth voltage. Therefore, the output voltage of the comparator switches from the second to the fourth voltage when the voltage of a signal at the first input of the comparator rises above the first voltage, and the output voltage of the comparator switches from the fourth to the second voltage when the voltage of the signal at the first input of the comparator falls below the third voltage.

Abstract: A shift register comprises a plurality of amorphous silicon thin-film transistors configured in a plurality of register cells through which data is shifted through a plurality of amorphous silicon thin-film floating-gate transistors. In the event power is cutoff or lost, the floating gate transistors non-volatilely store the data which can be recovered or restored when power is subsequently turned on. Each cell comprises two stages in which data signals are written before being input into the next stage and next cell. A clock generator receives clocking signals for controlling the shifting of data through the register.

Abstract: A battery-powered magnetic pen has an oscillator for generating a magnetic field at a contact frequency and a proximity frequency. The oscillator is connected to a resettable timer. The pen also includes a tip switch that is actuated in response to the pen being brought into engagement with an object and disengaged from the object. The tip switch is connected to a pulse generator and to the oscillator. Each time the pen is brought into engagement with an object, the pulse generator resets the timer to initiate the timing of a time out period. Assuming the oscillator is off, the first time the pen contacts an object, the resetting causes the oscillator to be turned on. So long as the oscillator is on, the opening and closing of the tip switch causes the oscillator to switch between the contact frequency and the proximity frequency. Should the timer reach the end of a predetermined time out period, the oscillator is shut off.

Abstract: A battery-powered, magnetic-pen oscillator includes a circuit having a first transistor arranged in a common emitter configuration. A feedback loop includes a transformer and the transistor that produce a loop phase shift of zero degrees and a loop gain of one to cause oscillation, and additionally creates the magnetic field emitted by the pen. A second transistor provides current mirror biasing for the first transistor and determines the amount of current flowing through the first transistor.

Abstract: The present off/on delay circuit operates within the power supply of a microcomputer system to interrupt transfer of regulated DC voltage to the system microcomputer and attachments in respect to indications of power disturbance and system switch status produced in the supply. Upon termination of such indications, this circuit selectively delays reappearance of regulated DC voltage to the level required for system operation so that whenever the microcomputer resets, the attachments must also reset; thereby preventing lockout impasses in the system rebooting process. The circuit operates in response to a plurality of DC voltage indications in the power supply, including at least an indication distinguishing the state of AC source power as either good or bad, and an indication distinguishing the state of a manually operable system power switch as either on or off.

Abstract: A bandgap reference voltage generator consists of a plurality of transistors with the same geometry. This circuit provides a stable temperature-compensated low reference voltage on the order of two volts.