Abstract: A system and/or method for processing information is disclosed that has at least one processor; a register file associated with the processor, the register file sliced into a plurality of STF blocks having a plurality of STF entries, and in an embodiment, each STF block is further partitioned into a plurality of sub-blocks, each sub-block having a different portion of the plurality of STF entries; and a plurality of execution units configured to read data from and write data to the register file, where the plurality of execution units are arranged in one or more execution slices. In one or more embodiments, the system is configured so that each execution slice has a plurality of STF blocks, and alternatively or additionally, each of the plurality of execution units in a single execution slice is assigned to write to one, and preferably only one, of the plurality of STF blocks.

Abstract: A system and/or method for processing information is disclosed that has at least one processor; a register file associated with the processor, the register file sliced into a plurality of STF blocks having a plurality of STF entries, and in an embodiment, each STF block is further partitioned into a plurality of sub-blocks, each sub-block having a different portion of the plurality of STF entries; and a plurality of execution units configured to read data from and write data to the register file, where the plurality of execution units are arranged in one or more execution slices. In one or more embodiments, the system is configured so that each execution slice has a plurality of STF blocks, and alternatively or additionally, each of the plurality of execution units in a single execution slice is assigned to write to one, and preferably only one, of the plurality of STF blocks.

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

Abstract: A memory circuit includes a global read bit line, a global read bit line latch, and a plurality of sub-arrays, each of which includes first and second local read bit lines, first and second local write bit lines, and first and second pluralities of memory cells interconnected, respectively, with the first and second local read bit lines and the first and second local write bit lines. The local read bit lines are decoupled from the local write bit lines. A local multiplexing block is interconnected with the first and second local read bit lines and is configured to ground the first and second local read bit lines upon assertion of a SLEEP signal, and to selectively interconnect the local read bit lines to the global read bit line. A global multiplexing block is interconnected with the global read bit line and is configured to maintain the global read bit line in a substantially discharged state upon assertion of the SLEEP signal and to interconnect the global read bit line to the global read bit line latch.

Abstract: Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.

Abstract: A circuit permits a user to present signals to control the flow of data from a first-type cell to a second-type cell. The circuit is susceptible to loading each cell individually, as well as loading cells by means of scanning input in a series through a low order cell to a higher order cell. The circuit may be copied as a series of cells wherein a bit held in each first-type cell is copied to the next higher second-type cell.

Abstract: A method, system and apparatus for detecting soft errors in non-dataflow circuits. In a preferred embodiment, input is received at a latch system. The latch system consists of two pairs of latches. The second pair of latches is parallel to the first pair of latches. Both pairs of latches capture the input. However, the second pair of latches captures the input later in time relative to the first pair of latches latch. The captured input is then transferred from the first latch in each pair of latches to the second latch in each pair of latches. A comparison is made of the input in the two second latches. If the input captured in the two second latches is not the same, then a message is sent to a recovery unit.

Abstract: An eight-transistor tri-state driver. The tri-state driver implements multiple cascade structures where each cascade structure may refer to a pair of complementary transistors serially connected. Each cascade structure may include a p-conductivity type transistor serially connected to a n-conductivity type transistor. By implementing cascade structures in a tri-state driver, there is a lower peak current consumption, a reduced slew rate as well as a reduction in the amount of layout area used in comparison to the classic tri-state drivers.

Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.

Abstract: A hybrid shift register latch which uses static memory cells for system operations and a dynamic memory cell for testing operations only. An L1 storage element and an L2 storage element are provided in an array cell. The L1 storage element comprises a static random access memory cell. The L1 storage element is used during system and testing operation of the array cell. The L2 storage element comprises a dynamic random access memory cell. The L2 storage element is used only during testing operation of the array cell.

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract: A register file is often used within integrated circuitry to temporarily hold data. Sometimes this data needs to be retained within the register file for a period of time, such as when there is a stall operation. Conventional register files have utilized a hold multiplexor to perform such a stall operation. The multiplexor however inserts a delay that is undesirable in high performance integrated circuitry. The multiplexor is replaced with a tri-state inverter coupled to the global bit line of the register file, which minimizes this additional delay from the register file data access time.

Abstract: An apparatus and method are provided for reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. The apparatus and method provide a mechanism to write the consecutive entries by only having a 4 to 16 decode of one address. In addition, the apparatus and method provide a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

Abstract: Reading a plurality of consecutive entries and writing a plurality of consecutive entries with only one read address and one write address using a 2Read/2Write register file is provided. In one exemplary embodiment, a 64 entry register file array is partitioned into four sub-arrays. Each sub-array contains sixteen entries having one or more 2Read/2Write SRAM cells. A mechanism to write the consecutive entries by only having a 4 to 16 decode of one address is also provided. In addition, a mechanism for reading data from the register file array using a starting read word address and two read word lines generated based on the starting read word address is provided. The two read word lines are used to access the two read ports of the entries in the sub-arrays.

Abstract: Techniques are provided for a register file cell that includes a primary storage portion configured to store a first value, and a secondary storage portion that is coupled to the primary storage portion. The secondary storage portion is configured to function as a scan latch during a test operation, and is further configured to store a second value during normal operation. The second value is a duplicate of the first value. The cell further includes an error detection portion that is coupled to the primary storage portion and the secondary storage portion and is configured to indicate a difference between the first value and the second value, caused by a soft error.

Abstract: An apparatus, system and method for quickly determining an oldest instruction in a non-moving instruction queue of a processor are provided. Particularly, instructions are stored, one at a time at a clock cycle, in the non-moving queue. At every clock cycle, a present status of the instructions in the queue is recorded. Using the present status of the instructions in the queue in conjunction with previously recorded statuses of the instructions, the oldest instruction in the queue is determined. The status of the instructions in the queue includes whether or not the instruction has been issued for execution as well as whether or not it is known that the issued instruction has been accepted for execution.

Abstract: An apparatus and method for speeding up access time of a large register file with wrap capability are provided. With the apparatus and method, the 2:1 multiplexers in conventional register file systems are eliminated from the circuit configuration and instead, additional primary multiplexers are provided for half of the addresses, e.g., the first four sub-arrays of the register file for which the wrap capability is needed. These additional primary multiplexers receive the read address and a shifted read word line signal. The other primary multiplexer receives the read address and an unshifted read word line signal. The outputs from the shifted and non-shifted primary multiplexers are provided to a set of secondary multiplexers which multiplex bits from the outputs of the shifted and non-shifted primary multiplexers to generate the read addresses to be used by the multiple read/write register file system.

Abstract: A method and apparatus for ensuring proper operation of a dynamic circuit is provided. A dynamic circuit instance has a plurality of outputs connected to a respective one of a plurality of leakage detector circuits. An output of each leakage detector circuit is connected with a respective one of a plurality of keeper circuits that reside at the dynamic circuit. Each of the plurality of keeper circuits has a unique size ratio with respect to a logic element size of the dynamic circuit.