Patents by Inventor Sameer Pendharkar

Sameer Pendharkar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Fast switching IGBT with embedded emitter shorting contacts and method for making same
    Patent number: 9385196
    Abstract: Integrated circuits are presented having high voltage IGBTs with integral emitter shorts and fabrication processes using wafer bonding or gown epitaxial silicon for controlled drift region thickness and fast switching speed.
    Type: Grant
    Filed: September 12, 2012
    Date of Patent: July 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Jacek Korec, John Manning Savidge Neilson, Sameer Pendharkar
  • Process for forming driver for normally on III-nitride transistors to get normally-off functionality
    Patent number: 9379022
    Abstract: A semiconductor device includes a depletion mode GaN FET and an integrated driver/cascode IC. The integrated driver/cascode IC includes an enhancement mode cascoded NMOS transistor which is connected in series to a source node of the GaN FET. The integrated driver/cascode IC further includes a driver circuit which conditions a gate input signal and provides a suitable digital waveform to a gate node of the cascoded NMOS transistor. The cascoded NMOS transistor and the driver circuit are formed on a same silicon substrate.
    Type: Grant
    Filed: June 22, 2015
    Date of Patent: June 28, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • High Voltage Lateral DMOS Transistor with Optimized Source-Side Blocking Capability
    Publication number: 20160163855
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 9, 2016
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • High Voltage Lateral DMOS Transistor with Optimized Source-Side Blocking Capability
    Publication number: 20160163828
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Application
    Filed: February 2, 2016
    Publication date: June 9, 2016
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Method for forming avalanche energy handling capable III-nitride transistors
    Patent number: 9356117
    Abstract: A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1?xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.
    Type: Grant
    Filed: April 16, 2015
    Date of Patent: May 31, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • INTEGRATION OF HEAT SPREADER FOR BEOL THERMAL MANAGEMENT
    Publication number: 20160093551
    Abstract: A microelectronic device includes a heat spreader layer on an electrode of a component and a metal interconnect on the heat spreader layer. The heat spreader layer is disposed above a top surface of a substrate of the semiconductor device. The heat spreader layer is 100 nanometers to 3 microns thick, has an in-plane thermal conductivity of at least 150 watts/meter-° K, and an electrical resistivity less than 100 micro-ohm-centimeters.
    Type: Application
    Filed: September 28, 2014
    Publication date: March 31, 2016
    Applicant: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Archana Venugopal, Marie Denison, Luigi Colombo, Sameer Pendharkar
  • High voltage lateral DMOS transistor with optimized source-side blocking capability
    Patent number: 9299832
    Abstract: An integrated circuit and method having an extended drain MOS transistor with a buried drift region, a drain diffused link, a channel diffused link, and an isolation link which electrically isolated the source, where the isolation diffused link is formed by implanting through segmented areas to dilute the doping to less than two-thirds the doping in the drain diffused link.
    Type: Grant
    Filed: December 11, 2014
    Date of Patent: March 29, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Sinker with a reduced width
    Patent number: 9293357
    Abstract: The width of a heavily-doped sinker is substantially reduced by forming the heavily-doped sinker to lie in between a number of closely-spaced trench isolation structures, which have been formed in a semiconductor material. During drive-in, the closely-spaced trench isolation structures significantly limit the lateral diffusion.
    Type: Grant
    Filed: July 2, 2012
    Date of Patent: March 22, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Binghua Hu, Sameer Pendharkar, Guru Mathur, Takehito Tamura
  • Drain Extended CMOS with Counter-Doped Drain Extension
    Publication number: 20160079392
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Application
    Filed: November 23, 2015
    Publication date: March 17, 2016
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • TRENCH GATE TRENCH FIELD PLATE VERTICAL MOSFET
    Publication number: 20160071923
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Application
    Filed: November 18, 2015
    Publication date: March 10, 2016
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • HIGH VOLTAGE DEPLETION MODE N-CHANNEL JFET
    Publication number: 20160043236
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Application
    Filed: October 26, 2015
    Publication date: February 11, 2016
    Inventors: Philip Leland HOWER, Sameer PENDHARKAR, Marie DENISON
  • Trench gate trench field plate semi-vertical semi-lateral MOSFET
    Patent number: 9240465
    Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.
    Type: Grant
    Filed: August 7, 2015
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • Vertical trench MOSFET device in integrated power technologies
    Patent number: 9240446
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 19, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Guru Mathur, Marie Denison, Sameer Pendharkar
  • Drain extended CMOS with counter-doped drain extension
    Patent number: 9231054
    Abstract: An integrated circuit containing a diode with a drift region containing a first dopant type plus scattering centers. An integrated circuit containing a DEMOS transistor with a drift region containing a first dopant type plus scattering centers. A method for designing an integrated circuit containing a DEMOS transistor with a counter doped drift region.
    Type: Grant
    Filed: November 6, 2013
    Date of Patent: January 5, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philipp Steinmann, Amitava Chatterjee, Sameer Pendharkar
  • Trench gate trench field plate vertical MOSFET
    Patent number: 9224854
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define vertical drift regions of the transistor, so that each vertical drift region is bounded on at least two opposite sides by the deep trench structures. The deep trench structures are spaced so as to form RESURF regions for the drift region. Trench gates are formed in trenches in the substrate over the vertical drift regions. The body regions are located in the substrate over the vertical drift regions.
    Type: Grant
    Filed: October 3, 2013
    Date of Patent: December 29, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Marie Denison, Sameer Pendharkar, Guru Mathur
  • TRENCH GATE TRENCH FIELD PLATE SEMI-VERTICAL SEMI-LATERAL MOSFET
    Publication number: 20150349092
    Abstract: A semiconductor device has a vertical drain extended MOS transistor with deep trench structures to define a vertical drift region and at least one vertical drain contact region, separated from the vertical drift region by at least one instance of the deep trench structures. Dopants are implanted into the vertical drain contact regions and the semiconductor device is annealed so that the implanted dopants diffuse proximate to a bottom of the deep trench structures. The vertical drain contact regions make electrical contact to the proximate vertical drift region at the bottom of the intervening deep trench structure. At least one gate, body region and source region are formed above the drift region at, or proximate to, a top surface of a substrate of the semiconductor device. The deep trench structures are spaced so as to form RESURF regions for the drift region.
    Type: Application
    Filed: August 7, 2015
    Publication date: December 3, 2015
    Inventors: Marie DENISON, Sameer PENDHARKAR, Guru MATHUR
  • High voltage depletion mode N-channel JFET
    Patent number: 9202692
    Abstract: An integrated circuit and method having a JFET with a buried drift layer and a buried channel in which the buried channel is formed by implanting through segmented implant areas so that the doping density of the buried channel is between 25 percent and 50 percent of the doping density of the buried drift layer.
    Type: Grant
    Filed: December 17, 2014
    Date of Patent: December 1, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Philip Leland Hower, Sameer Pendharkar, Marie Denison
  • Method to form stepped dielectric for field plate formation
    Patent number: 9196692
    Abstract: A semiconductor device is formed with a stepped field plate over at least three sequential regions in which a total dielectric thickness under the stepped field plate is at least 10 percent thicker in each region compared to the preceding region. The total dielectric thickness in each region is uniform. The stepped field plate is formed over at least two dielectric layers, of which at least all but one dielectric layer is patterned so that at least a portion of a patterned dielectric layer is removed in one or more regions of the stepped field plate.
    Type: Grant
    Filed: May 7, 2015
    Date of Patent: November 24, 2015
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Sameer Pendharkar, Naveen Tipirneni
  • VERTICAL TRENCH MOSFET DEVICE IN INTEGRATED POWER TECHNOLOGIES
    Publication number: 20150325638
    Abstract: A semiconductor device having a vertical drain extended MOS transistor may be formed by forming deep trench structures to define at least one vertical drift region bounded on at least two opposite sides by the deep trench structures. The deep trench structures include dielectric liners. The deep trench structures are spaced so as to form RESURF regions for the drift region. Vertical gates are formed in vertically oriented gate trenches in the dielectric liners of the deep trench structures, abutting the vertical drift regions. A body implant mask for implanting dopants for the transistor body is also used as an etch mask for forming the vertically oriented gate trenches in the dielectric liners.
    Type: Application
    Filed: July 23, 2015
    Publication date: November 12, 2015
    Inventors: Guru MATHUR, Marie DENISON, Sameer PENDHARKAR
  • LOW COST TRANSISTORS
    Publication number: 20150325578
    Abstract: An integrated circuit containing an analog MOS transistor has an implant mask for a well which blocks well dopants from two diluted regions at edges of the gate, but exposes a channel region to the well dopants. A thermal drive step diffuses the implanted well dopants across the two diluted regions to form a continuous well with lower doping densities in the two diluted regions. Source/drain regions are formed adjacent to and underlapping the gate by implanting source/drain dopants into the substrate adjacent to the gate using the gate as a blocking layer and subsequently annealing the substrate so that the implanted source/drain dopants provide a desired extent of underlap of the source/drain regions under the gate. Drain extension dopants and halo dopants are not implanted into the substrate adjacent to the gate.
    Type: Application
    Filed: July 20, 2015
    Publication date: November 12, 2015
    Inventors: Pinghai HAO, Sameer PENDHARKAR