Patents by Inventor Sampath K. V. Karikalan

Sampath K. V. Karikalan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9548251
    Abstract: A semiconductor package may include a substrate, and a semiconductor interposer having a cavity and a plurality of through semiconductor vias. The semiconductor interposer is situated over the substrate. An intra-interposer die is disposed within the cavity of the semiconductor interposer. A thermally conductive adhesive is disposed within the cavity and contacts the intra-interposer die. Additionally, a top die is situated over the semiconductor interposer. In one implementation, the semiconductor interposer is a silicon interposer. In another implementation, the semiconductor interposer is flip-chip mounted to the substrate such that the intra-interposer die disposed within the cavity faces the substrate. In yet another implementation, the cavity in the semiconductor interposer may extend from a top surface of the semiconductor interposer to a bottom surface of the semiconductor interposer and a thermal interface material may be disposed between the intra-interposer die and the substrate.
    Type: Grant
    Filed: January 12, 2012
    Date of Patent: January 17, 2017
    Assignee: Broadcom Corporation
    Inventors: Rezaur Rahman Khan, Sam Ziqun Zhao, Pieter Vorenkamp, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Xiangdong Chen
  • Publication number: 20160155728
    Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the, top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.
    Type: Application
    Filed: February 8, 2016
    Publication date: June 2, 2016
    Inventors: Sam Ziqun ZHAO, Rezaur Rahman KHAN, Pieter VORENKAMP, Sampath K.V. KARIKALAN, Kevin Kunzhong HU, Xiangdong CHEN
  • Patent number: 9349697
    Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.
    Type: Grant
    Filed: December 8, 2014
    Date of Patent: May 24, 2016
    Assignee: Broadcom Corporation
    Inventors: Lynn Ooi, Sampath K. V. Karikalan
  • Patent number: 9293393
    Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 22, 2016
    Assignee: Broadcom Corporation
    Inventors: Kevin Kunzhong Hu, Sam Ziqun Zhao, Rezaur Rahman Khan, Pieter Vorenkamp, Sampath K. V. Karikalan, Xiangdong Chen
  • Patent number: 9275976
    Abstract: There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: March 1, 2016
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 9153507
    Abstract: An exemplary implementation of the present disclosure includes a testable semiconductor package that includes an active die having interface contacts and dedicated testing contacts. An interposer is situated adjacent a bottom surface of the active die, the interposer providing electrical connections between the interface contacts and a bottom surface of the testable semiconductor package. At least one conductive medium provides electrical connection between at least one of the dedicated testing contacts and a top surface of the testable semiconductor package. The at least one conductive medium can be coupled to a package-top testing connection, which may include a solder ball.
    Type: Grant
    Filed: January 31, 2012
    Date of Patent: October 6, 2015
    Assignee: BROADCOM CORPORATION
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20150221603
    Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.
    Type: Application
    Filed: December 8, 2014
    Publication date: August 6, 2015
    Applicant: Broadcom Corporation
    Inventors: Lynn Ooi, Sampath K.V. Karikalan
  • Patent number: 9059179
    Abstract: There are disclosed herein various implementations of semiconductor packages including a bridge interposer. One exemplary implementation includes a first active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The semiconductor package also includes a second active die having a first portion situated over the bridge interposer, and a second portion not situated over the bridge interposer. The second portion of the first active die and the second portion of the second active die include solder balls mounted on a package substrate, and are configured to communicate electrical signals to the package substrate utilizing the solder balls and without utilizing through-semiconductor vias (TSVs).
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: June 16, 2015
    Assignee: Broadcom Corporation
    Inventors: Sampath K. V. Karikalan, Sam Ziqun Zhao, Kevin Kunzhong Hu, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 9041171
    Abstract: An exemplary implementation of the present disclosure includes a programmable interposer having top and bottom interface electrodes and conductive particles interspersed within the programmable interposer. The conductive particles are capable of forming an aligned configuration between the top and bottom interface electrodes in response to application of an energy field to the programmable interposer so as to electrically connect the top and bottom interface electrodes. The conductive particles can have a conductive outer surface. Also, the conductive particles can be spherical. The conductive particles can be within a bulk material in an interface layer in the programmable interposer, and the bulk material can be cured to secure programmed paths between the top and bottom interface electrodes.
    Type: Grant
    Filed: December 29, 2011
    Date of Patent: May 26, 2015
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 9013041
    Abstract: There are disclosed herein various implementations of semiconductor packages including an interposer without through-semiconductor vias (TSVs). One exemplary implementation includes a first active die situated over an interposer. The interposer includes an interposer dielectric having intra-interposer routing traces. The first active die communicates electrical signals to a package substrate situated below the interposer utilizing the intra-interposer routing traces and without utilizing TSVs. In one implementation, the semiconductor package includes a second active die situated over the interposer, the second active die communicating electrical signals to the package substrate utilizing the intra-interposer routing traces and without utilizing TSVs. Moreover, in one implementation, the first active die and the second active die communicate chip-to-chip signals through the interposer.
    Type: Grant
    Filed: December 28, 2011
    Date of Patent: April 21, 2015
    Assignee: Broadcom Corporation
    Inventors: Sampath K. V. Karikalan, Sam Ziqun Zhao, Kevin Kunzhong Hu, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 8928128
    Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.
    Type: Grant
    Filed: February 27, 2012
    Date of Patent: January 6, 2015
    Assignee: Broadcom Corporation
    Inventors: Sampath K. V. Karikalan, Kevin Kunzhong Hu, Sam Ziqun Zhao, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 8907488
    Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.
    Type: Grant
    Filed: January 16, 2013
    Date of Patent: December 9, 2014
    Assignee: Broadcom Corporation
    Inventors: Lynn Ooi, Sampath K V Karikalan
  • Patent number: 8872321
    Abstract: One implementation of present disclosure includes a semiconductor package stack. The semiconductor package stack includes an upper package coupled to a lower package by a plurality of solder balls. The semiconductor package stack also includes a lower active die situated in a lower package substrate in the lower package. The lower active die is thermally coupled to a heat spreader in the upper package by a thermal interface material. An upper active die is situated in an upper package substrate in the upper package, the upper package substrate being situated over the heat spreader. The thermal interface material can include an array of aligned carbon nanotubes within a filler material. The heat spreader can include at least one layer of metal or metal alloy. Furthermore, the heat spreader can be connected to ground or a DC voltage source. The plurality of solder balls can be situated under the heat spreader.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: October 28, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Rezaur Rahman Khan, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Pieter Vorenkamp, Xiangdong Chen
  • Patent number: 8791533
    Abstract: There are disclosed herein various implementations of semiconductor packages having an interposer configured for magnetic signaling. One exemplary implementation includes a die transmit pad in an active die for transmitting a magnetic signal corresponding to a die electrical signal produced by the active die, and an interposer magnetic tunnel junction (MTJ) pad in the interposer for receiving the magnetic signal. A sensing circuit is coupled to the interposer MTJ pad for producing a receive electrical signal corresponding to the magnetic signal. In one implementation, the sensing circuit is configured to sense a resistance of the interposer MTJ pad and to produce the receive electrical signal according to the sensed resistance.
    Type: Grant
    Filed: January 30, 2012
    Date of Patent: July 29, 2014
    Assignee: Broadcom Corporation
    Inventors: Xiangdong Chen, Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp
  • Publication number: 20140183748
    Abstract: Embodiments described herein generally relate to connections for integrated circuit (IC) dies. For example, in an embodiment an integrated circuit (IC) die is provided. The IC die includes a plurality of clusters of pads formed on a surface of the IC die, each cluster being associated with a respective circuit formed in the IC die. Each cluster includes a plurality of micropads each electrically coupled to the circuit associated with the cluster through a respective via and a sacrificial pad coupled to the circuit through the plurality of micropads, the sacrificial pad being larger than each of the micropads.
    Type: Application
    Filed: January 16, 2013
    Publication date: July 3, 2014
    Applicant: Broadcom Corporation
    Inventors: Lynn Ooi, Sampath K. V. Karikalan
  • Patent number: 8749072
    Abstract: There are disclosed herein various implementations of semiconductor packages having a selectively conductive film interposer. In one such implementation, a semiconductor package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, a selectively conductive film interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The selectively conductive film interposer may be configured to serve as an interposer and to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors.
    Type: Grant
    Filed: February 24, 2012
    Date of Patent: June 10, 2014
    Assignee: Broadcom Corporation
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20140151900
    Abstract: An exemplary implementation of the present disclosure includes a stacked package having a top die from a top reconstituted wafer situated over a bottom die from a bottom reconstituted wafer. The top die and the bottom die are insulated from one another by an insulation arrangement. The top die and the bottom die are also interconnected through the insulation arrangement. The insulation arrangement can include a top molding compound that flanks the top die and a bottom molding compound that flanks the bottom die. The top die and the bottom die can be interconnected through at least the top molding compound. Furthermore, the top die and the bottom die can be interconnected through a conductive via that extends within the insulation arrangement.
    Type: Application
    Filed: February 7, 2014
    Publication date: June 5, 2014
    Applicant: BROADCOM CORPORATION
    Inventors: Kevin Kunzhong HU, Sam Ziqun Zhao, Rezaur Rahman Khan, Pieter Vorenkamp, Sampath K.V. Karikalan, Xiangdong Chen
  • Publication number: 20130221500
    Abstract: There are disclosed herein various implementations of a system-in-package with integrated socket. In one such implementation, the system-in-package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, an interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The interposer is configured to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors. In addition, a socket encloses the first and second active dies and the interposer, the socket being electrically coupled to at least one of the first active die, the second active die, and the interposer.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20130221525
    Abstract: There are disclosed herein various implementations of semiconductor packages having a selectively conductive film interposer. In one such implementation, a semiconductor package includes a first active die having a first plurality of electrical connectors on a top surface of the first active die, a selectively conductive film interposer situated over the first active die, and a second active die having a second plurality of electrical connectors on a bottom surface of the second active die. The selectively conductive film interposer may be configured to serve as an interposer and to selectively couple at least one of the first plurality of electrical connectors to at least one of the second plurality of electrical connectors.
    Type: Application
    Filed: February 24, 2012
    Publication date: August 29, 2013
    Applicant: BROADCOM CORPORATION
    Inventors: Sam Ziqun Zhao, Kevin Kunzhong Hu, Sampath K. V. Karikalan, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen
  • Publication number: 20130221499
    Abstract: There are disclosed herein various implementations of a shield interposer situated between a top active die and a bottom active die for shielding the active dies from electromagnetic noise. One implementation includes an interposer dielectric layer, a through-silicon via (TSV) within the interposer dielectric layer, and an electromagnetic shield. The TSV connects the electromagnetic shield to a first fixed potential. The electromagnetic shield may include a grid of conductive layers laterally extending across the shield interposer. The shield interposer may also include another electromagnetic shield connected to another fixed potential.
    Type: Application
    Filed: February 27, 2012
    Publication date: August 29, 2013
    Applicant: Broadcom Corporation
    Inventors: Sampath K.V. Karikalan, Kevin Kunzhong Hu, Sam Ziqun Zhao, Rezaur Rahman Khan, Pieter Vorenkamp, Xiangdong Chen