Abstract: Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.

Abstract: An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration.

Abstract: Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.

Abstract: Systems, methods and articles of manufacture are disclosed for recording events occurring in a virtual world. In one embodiment, properties of events previously recorded and/or attended by a user may be identified. Recording criteria for the user may be derived from the identified properties. Upon identifying an event satisfying the recording criteria, the event may be recorded. The recorded event may be played back at the convenience of the user.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: Mechanisms are provided for performing placement of cells in a design of a semiconductor device. An initial design of the semiconductor device is generated, the initial design comprising a first placement of cells. A preferred direction of placement associated with the cells is determined. The preferred direction is a direction along which spreading of the cells is preferred. A second design of the semiconductor device is generated by modifying the first placement of the cells to generate a second placement of cells, different from the first placement cells, based on the preferred direction of placement associated with the cells.

Abstract: A netlist for an integrated circuit design is constrained by virtual or “soft” pins to control or stabilize the placement of logic such as an architectural logic path. One soft pin is inserted at a fixed location proximate an input net of the path and is interconnected with the input net, and another is inserted at a fixed location proximate the output net and is interconnected with the output net. Cell placement is then optimized while maintaining the virtual pins at their fixed locations. More than two virtual pins may be inserted to bound a cluster of logic. The virtual pins may lie along the input/output nets. Pseudo-net weights are assigned to pseudo-nets formed between a cell and the virtual pins, and the pseudo-net weight can be increased for each placement iteration.

Abstract: Spare cells are inserted in a region of an integrated circuit design based on a logic complexity of the region. The logic complexity can be computed based on the number of reachable states of digital logic in the region, and can be correlated to a desired spare cell insertion rate which is then compared to the actual spare cell utilization in the region. The target spare cell rate can further based on logic complexity values for neighboring regions with a proximity penalty.

Abstract: Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement.

Abstract: Bit stacks of an integrated circuit design are identified in a netlist by analyzing cell clusters. Candidate bit stacks are generated for each cluster using cone tracing, and wirelength costs are calculated for the candidate bit stacks based on the cells' locations from a previous (e.g., global) placement. The bit stack partition having a minimum total wirelength cost is selected for the final bit stacks. The invention can find K bit stacks in a cell cluster having N input cells and M output cells, where K, N and M are all different. The method is advantageously made timing aware by weighting connections between cells using weights based on timing information. Once the final bit stacks have been identified, the information can be included in the netlist and passed to a datapath placer for optimized placement.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.

Abstract: A datapath extraction tool uses machine-learning models to selectively classify clusters of cells in an integrated circuit design as either datapath logic or non-datapath logic based on cluster features. A support vector machine and a neural network can be used to build compact and run-time efficient models. A cluster is classified as datapath if both the support vector machine and the neural network indicate that it is datapath-like. The cluster features may include automorphism generators for the cell clusters, or physical information based on the cell locations from a previous (e.g., global) placement, such as a ratio of a total cell area for a given cluster to a half-perimeter of a bounding box for the given cluster.

Abstract: Datapath placement defines tiers for placement sets of a cell cluster, assigns cells to the tiers constrained by the datapath width, and then orders cells within each tier. Clusters are identified using machine-learning based datapath extraction. Datapath width is determined by computing a size of a bounding box for cells in the cluster. Placement sets are identified using a breadth-first search beginning with input cells for the cluster. Tiers are initially defined using logic depth assignment. A cell may be assigned to a tier by pulling the cell from the next higher tier to fill an empty location or by pushing an excess cell into the next higher tier. Cells are ordered within each tier using greedy cell assignment according to a wirelength cost function. The datapath placement can be part of an iterative process which applies spreading constraints to the cluster based on computed congestion information.

Abstract: An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration.

Abstract: Decoupling capacitors (dcaps) are placed in an IC design by assigning different dcap utilization rates to logic cones, applying the rates to corresponding dcap regions surrounding cells in the cones, identifying any overlap of regions from different logic cones, and inserting a dcap at the overlapping region having the highest dcap utilization rate. The best location for the dcap is computed using a hypergraph wherein the cells are edges and the regions are nodes. Any node that is dominated by another node is removed and its edge is extended to the dominating node. The dcap is inserted in the region having the most edges (the edges can be weighted). The process is repeated iteratively, updating the hypergraph by removing nodes connected to dcap location, and inserting the next dcap at a region corresponding to the node which then has the greatest number of connected edges.

Abstract: An automated method for aligning a critical datapath in an integrated circuit design inserts an artificial alignment net in the netlist which interconnects all cells in the bit stack of the datapath. The cells are placed using a wirelength optimization which assigns weights to wire sections based on the alignment direction. The rate of change of the alignment weighting value can vary during different stages of global placement. The invention is particularly suited for a force-directed placer which uses a linear system solver to obtain a globally optimum solution for placement of the cells having some overlap among the cells, and thereafter spreads the cells to reduce the overlap. Pseudo nets are also inserted which interconnect a cell and an expected location of the cell after spreading for that iteration.