Abstract: A system and method is disclosed for providing multi-point calibration of an adaptive voltage scaling (AVS) system. A plurality of Reference Calibration Codes (RCCs) within a multi-point calibration table is provided. Each code is associated with one of the clock frequencies of the adaptive voltage scaling (AVS) system. The present invention provides multi-point calibration by calibrating a Reference Calibration Code (RCC) for each operating point (clock frequency) of the adaptive voltage scaling (AVS) system.

Abstract: A method to assist in deciding whether or not an ATM PNNI network link is able to sustain a new connection is described. The method comprises, if the link is not within an LCN exhaustion state and the new connection requests more bandwidth than is advertised as being available upon the link for the new connection's service category, regarding the bandwidth available for the new connection as a sum. The sum comprises addition of: 1) the advertised available bandwidth and 2) the total bandwidth reserved on the link for connections having lower priority than the new connection enhanced by over-subscription for the service category.

Abstract: A method and system for selecting connections to bump based on priority in a network. The present invention describes a method for selecting connections to bump in a network to accommodate an incoming connection. The method begins by receiving an incoming connection that is associated with a priority level and a bandwidth group. A plurality of existing connections is indexed by priority level and bandwidth group. A required bandwidth is calculated that is necessary to support the incoming connection. Then, a single existing connection is selected to be released from the plurality of existing connections that is associated with a lower priority and a higher bandwidth group than the incoming connection. If a single connection cannot be selected, then at least one existing connection is selected to be released having a lower priority level and at least the same bandwidth group than that of the incoming connection.

Abstract: A method is described that involves sending a positive imposter response as a consequence of a status request message having been received. The status request message refers to a network connection. The status request message was sent to the networking system to ask the networking system to inquire into the status of the network connection.

Abstract: There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

Abstract: There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.

Abstract: A method, and apparatus to transmit an ATM data message from a source node to a destination node, and reflect at least a portion of the data back t where it is compared to the transmitted data. The destination node includes a reflection circuit service located at a specific selector code address, and the destination node listens for a transmission to the specific selector code for reflecting the portion of received data in a subsequent data message for the connection. The source node addresses a setup message to the destination node containing the specific selector code, and compares the transmitted message with the received message. The source node also includes a method and apparatus to send alternatively trace and path trace information as an attachment to a transmitted message, receive the reflected information element, and pass hop data contained within the information element to a user interface for presentation to a user.

Abstract: A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.

Abstract: A voltage controller (150), the controller comprising: a voltage comparator (700) operative to provide a digital error signal (152); a compensator (300) operative to determine a digital control signal (154) based on said provided error signal; and a modulator (400) operative to provide a power control signal (156) based on said determined digital control signal, wherein said comparator, said compensator, and said modulator are implemented entirely with digital logic gates.

Abstract: A method and system for selecting connections to bump based on priority in a network. The present invention describes a method for selecting connections to bump in a network to accommodate an incoming connection. The method begins by receiving an incoming connection that is associated with a priority level and a bandwidth group. A plurality of existing connections is indexed by priority level and bandwidth group. A required bandwidth is calculated that is necessary to support the incoming connection. Then, a single existing connection is selected to be released from the plurality of existing connections that is associated with a lower priority and a higher bandwidth group than the incoming connection. If a single connection cannot be selected, then at least one existing connection is selected to be released having a lower priority level and at least the same bandwidth group than that of the incoming connection.

Abstract: There is disclosed control circuitry for adjusting a power supply level, VDD, of a digital processing component having varying operating frequencies. The control circuitry comprises N delay cells and power supply adjustment circuitry. The N delay cells are coupled in series, each of which has a delay D determined by a value of VDD, such that a clock edge applied to an input of a first delay cell ripples sequentially through the N delay cells. The power supply adjustment circuitry capable of adjusting VDD and is operable to (i) monitor outputs of at least a K delay cell and a K+1 delay cell, (ii) determine that the clock edge has reached an output of the K delay cell and has not reached an output of the K+1 delay cell, and (iii) generate a control signal capable of adjusting VDD in response thereto.

Abstract: There is disclosed a digital circuit comprising a digital processing component, an adjustable power supply and power supply adjustment circuitry. The digital processing component is capable of operating at a plurality of selected clock frequencies, wherein a maximum delay time of a critical path in the digital processing component is determined by a level of a power supply, VDD, of the digital processing component. The adjustable power supply is capable of supplying VDD to the digital processing component. The power supply adjustment circuitry is operable to receive a first selected clock signal and adjusts the level of VDD such that the maximum delay time of the critical path of the digital processing component is less than a pulse-width duration between a first clock edge of the first selected clock signal and a second clock edge of the first selected clock signal immediately following the first clock edge.

Abstract: A method for providing self-calibration for adaptively adjusting a power supply voltage in a digital processing system is provided that includes providing a nominal power supply voltage to the system as a power supply voltage. A regulator clock signal is propagated through a delay line. The delay line comprises a plurality of delay cells and is operable to function based on the nominal power supply voltage. A plurality of pairs of delay cells are sampled until a first and second delay cell are identified based on the first delay cell receiving the regulator clock signal and the second delay cell failing to receive the regulator clock signal at a specified time. A reference voltage is provided to the system as the power supply voltage. The system is operated using the first and second delay cells to determine whether to adjust the power supply voltage for the system.

Abstract: There is disclosed an adaptive voltage power supply that finely adjusts VDD to an optimum level. The adaptive voltage power supply comprises: 1) a first charging circuit capable of increasing a reference voltage on a charge capacitor in response to receipt of a first VDD control signal; 2) a second charging circuit capable of decreasing the reference voltage on the charge capacitor in response to receipt of a second VDD control signal; and 3) a power supply capable of receiving the reference voltage on the charge capacitor and generating an output power level, VDD, determined by a level of the reference voltage.