Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.

Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.

Abstract: In a method for forming an integrated structure, a top dielectric layer is formed over a top surface of a substrate. The top dielectric layer includes a plurality of vias that are formed through the top dielectric layer and extend into the substrate. A bottom dielectric layer is formed on a bottom surface of the substrate. An isolation opening and a plurality of contact openings are further formed in the bottom dielectric layer and the substrate, where the isolation opening passes through the bottom dielectric layer and extends from the bottom surface to the top surface of the substrate. The isolation opening is filled with an insulating layer to form an isolation trench. The plurality of contact openings are filled with a conductive layer to form a plurality of through silicon contacts (TSCs). A conductive plate is further formed over the bottom dielectric layer.

Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. A second dielectric layer is formed on an opposing second main surface of the substrate. A first via is formed in the second dielectric layer, and a first end of the first via extends into the substrate to be in contact with the TSC. A second via is formed in the second dielectric layer and a first end of the second via extends into the substrate. A metal line is formed over the second dielectric layer so as to be coupled to the first via and the second via.

Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. The substrate includes an opposing second main surface. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. An isolation trench is formed in the substrate to surround the conductive plate and spaced apart from the conductive plate. A second dielectric layer is formed on the second main surface of the substrate. A first plurality of vias are formed in the second dielectric layer that extend into the substrate and are connected to the TSC. A second plurality of vias are formed in the second dielectric layer that extend into the substrate and are not connected to the TSC.

Abstract: Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

Abstract: In a TSC structure, a first dielectric layer is formed over a first main surface of a substrate. The substrate includes an opposing second main surface. A TSC is formed in the first dielectric layer and the substrate so that the TSC passes through the first dielectric layer and extends into the substrate. A conductive plate is formed over the first dielectric layer and electrically coupled with the TSC. An isolation trench is formed in the substrate to surround the conductive plate and spaced apart from the conductive plate. A second dielectric layer is formed on the second main surface of the substrate. A first plurality of vias are formed in the second dielectric layer that extend into the substrate and are connected to the TSC. A second plurality of vias are formed in the second dielectric layer that extend into the substrate and are not connected to the TSC.

Abstract: Embodiments of staircase structures for three-dimensional (3D) memory devices double-sided routing are disclosed. In an example, a 3D memory device includes a substrate, a memory stack disposed above the substrate and including conductor/dielectric layer pairs stacked alternatingly, and an array of memory strings each extending vertically through an inner region of the memory stack. An outer region of the memory stack includes a first staircase structure disposed on the substrate and a second staircase structure disposed above the first staircase structure. First edges of the conductor/dielectric layer pairs in the first staircase structure along a vertical direction away from the substrate are staggered laterally away from the array of memory strings. Second edges of the conductor/dielectric layer pairs in the second staircase structure along the vertical direction away from the substrate are staggered laterally toward the array of memory strings.

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.

Abstract: Integrated circuits having resistor structures formed from a MIM capacitor material and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a capacitor area. The method includes depositing a capacitor material over the resistor area and the capacitor area of the semiconductor substrate. The method also includes forming a resistor structure from the capacitor material in the resistor area. Further, the method includes forming electrical connections to the resistor structure in the resistor area.

Abstract: Methods for fabricating MIM capacitors with low VCC or decoupling and analog/RF capacitors on a single chip and the resulting devices are provided. Embodiments include forming: first and second metal lines in a substrate; a first electrode over, but insulated from, the first metal line; a first high-k dielectric layer on the first electrode, the first high-k dielectric layer having a coefficient ?; a second electrode on the first high-k dielectric layer and over a portion of the first electrode; a second high-k dielectric layer on the second electrode, the second high-k dielectric layer having a coefficient ?? opposite in polarity but substantially equal in magnitude to ?; a third electrode on the second high-k dielectric layer over the entire first electrode; and a metal-filled via through a dielectric layer down to the first metal line, and a metal-filled via through the dielectric layer down to the second metal line.

Abstract: Integrated circuits including a MIMCAP device and methods of forming the integrated circuits are provided. An exemplary method of forming an integrated circuit including a MIMCAP device includes pre-determining a thickness of at least one of a bottom high-K layer or a top high-K layer of the MIMCAP device, followed by fabricating the MIMCAP device. The pre-determined thickness is established based upon a pre-determined TDDB lifetime for the MIMCAP device and a minimum target capacitance density at an applied voltage bias to be employed for the MIMCAP device. The MIMCAP device includes a bottom electrode and a dielectric layer disposed over the bottom electrode. The dielectric layer includes a stack of individual layers including the bottom high-K layer, the top high-K layer, and a lower-K layer sandwiched therebetween. At least one of the bottom high-K layer or the top high-K layer has the pre-determined thickness.

Abstract: An integrated circuit system includes a substrate, forming a gate over the substrate, forming a first drift region having a first counter diffused region and a source diffused region, the first drift region in the substrate adjacent a first side of the gate, and forming a second drift region having a second counter diffused region and a drain diffused region, the second drift region in the substrate adjacent a second side of the gate opposite the first side of the gate.

Abstract: An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.

Abstract: A p-channel flash memory is formed with a charge storage stack embedded in a hetero-junction layer in which a raised source/drain is formed. Embodiments include forming a dummy gate stack on a substrate, forming a layer on the substrate by selective epitaxial growth, on each side of the dummy gate stack, forming spacers on the layer, forming raised source/drains, removing the dummy gate stack, forming a cavity between the spacers, and forming a memory gate stack in the cavity. Different embodiments include forming the layer of a narrow bandgap material, a narrow bandgap layer under the spacers and a wide bandgap layer adjacent thereto, or a wide bandgap layer under the spacers, a narrow bandgap layer adjacent thereto, and a wide bandgap layer on the narrow bandgap layer.

Abstract: Methods for forming FIN-shaped field effect transistors (FINFETs) capable of withstanding high voltage applications and the resulting devices are disclosed. Embodiments include forming a source and a drain on a substrate, forming a thin body (FIN) on the substrate and connecting the source and the drain, forming a gate over top and side surfaces of a first part of the FIN, thereby defining a drain-side FIN region of the FIN between the gate and the drain, and forming a shielding region over top and side surfaces of a second part of the FIN in the drain-side FIN region.

Abstract: A method of forming a device is presented. The method includes providing a structure having first and second regions. A diffusion barrier is formed between at least a portion of the first and second regions. The diffusion barrier comprises cavities that reduce diffusion of elements between the first and second regions.