Patents by Inventor Sang-bom Kang

Sang-bom Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200118926
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.
    Type: Application
    Filed: December 16, 2019
    Publication date: April 16, 2020
    Inventors: Eui Bok LEE, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
  • Patent number: 10510658
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.
    Type: Grant
    Filed: July 19, 2018
    Date of Patent: December 17, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Eui Bok Lee, Deok Young Jung, Sang Bom Kang, Doo-Hwan Park, Jong Min Baek, Sang Hoon Ahn, Hyeok Sang Oh, Woo Kyung You
  • Patent number: 10388563
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Grant
    Filed: August 3, 2017
    Date of Patent: August 20, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Rak Hwan Kim, Byung Hee Kim, Sang Bom Kang, Jong Jin Lee, Eun Ji Jung
  • Publication number: 20190181088
    Abstract: Semiconductor devices are provided. The semiconductor devices may include a substrate, a first insulating film on the substrate, a lower metal layer in the first insulating film, and a second insulating film on the first insulating film. The lower metal layer may be in the second insulating film, the second insulating film may include a lower surface facing the substrate and an upper surface that is opposite the lower surface, and the upper surface of the second insulating film may be upwardly convex. The semiconductor devices may further include a barrier dielectric film including a recess on the second insulating film, and a via metal layer that is in the recess of the barrier dielectric film and electrically connected with the lower metal layer.
    Type: Application
    Filed: July 19, 2018
    Publication date: June 13, 2019
    Inventors: Eui Bok Lee, Deok Young JUNG, Sang Bom KANG, Doo-Hwan PARK, Jong Min BAEK, Sang Hoon AHN, Hyeok Sang OH, Woo Kyung YOU
  • Publication number: 20180331218
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Application
    Filed: July 3, 2018
    Publication date: November 15, 2018
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-lk Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Publication number: 20180331100
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Application
    Filed: July 5, 2018
    Publication date: November 15, 2018
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Patent number: 10043902
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Grant
    Filed: December 9, 2015
    Date of Patent: August 7, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Publication number: 20180166334
    Abstract: A semiconductor device includes a lower layer, an upper layer on the lower layer, a contact between the lower layer and the upper layer, the contact electrically connects the lower layer and the upper layer, a capping pattern wrapping around the contact and covering an upper surface of the contact, a barrier layer wrapping around the capping pattern and covering a lower surface of the capping pattern and a lower surface of the contact, and an interlayer insulating layer between the lower layer and the upper layer, the interlayer insulating layer wrapping around the barrier layer and exposing an upper surface of the capping pattern, wherein the capping pattern includes a material having an etching selectivity with respect to an oxide.
    Type: Application
    Filed: August 3, 2017
    Publication date: June 14, 2018
    Inventors: Rak Hwan KIM, Byung Hee KIM, Sang Bom KANG, Jong Jin LEE, Eun Ji JUNG
  • Publication number: 20160233334
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Application
    Filed: December 9, 2015
    Publication date: August 11, 2016
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Patent number: 9305921
    Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
    Type: Grant
    Filed: December 10, 2014
    Date of Patent: April 5, 2016
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
  • Patent number: 9299811
    Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: March 29, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
  • Patent number: 9240323
    Abstract: A method of forming a semiconductor device can be provided by forming an opening that exposes a surface of an elevated source/drain region. The size of the opening can be reduced and a pre-amorphization implant (PAI) can be performed into the elevated source/drain region, through the opening, to form an amorphized portion of the elevated source/drain region. A metal-silicide can be formed from a metal and the amorphized portion.
    Type: Grant
    Filed: March 7, 2013
    Date of Patent: January 19, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Chung-Hwan Shin, Sang-Bom Kang, Dae-Yong Kim, Jeong-Ik Kim, Chul-Sung Kim, Je-Hyung Ryu, Sang-Woo Lee, Hyo-Seok Choi
  • Patent number: 9190410
    Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: November 17, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang
  • Patent number: 9112054
    Abstract: A semiconductor device and a method of manufacturing a semiconductor device are provided. In a method of manufacturing a semiconductor device, a gate structure is formed on a substrate. An epitaxial layer is formed on a top surface of the substrate adjacent to the gate structure. An elevated source/drain (ESD) layer and an impurity region are formed by implanting impurities and carbon in the epitaxial layer and an upper portion of the substrate using the gate structure as an ion implantation mask. A metal silicide layer is formed on the ESD layer.
    Type: Grant
    Filed: July 13, 2011
    Date of Patent: August 18, 2015
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kwan-Heum Lee, Wook-Je Kim, Soon-Wook Jung, Sang-Bom Kang, Ki-Hong Kim
  • Publication number: 20150147860
    Abstract: Semiconductor devices may include first and second fins that protrude from a substrate, extend in a first direction, and are separated from each other in the first direction. Semiconductor devices may also include a field insulating layer that is disposed between the first and second fins to extend in a second direction intersecting the first direction, an etch-stop layer pattern that is formed on the field insulating layer and a dummy gate structure that is formed on the etch-stop layer pattern.
    Type: Application
    Filed: October 21, 2014
    Publication date: May 28, 2015
    Inventors: Wook-Je Kim, Jae-Yup Chung, Jong-Seo Hong, Cheol Kim, Hee-Soo Kang, Hyun-Jo Kim, Hee-Don Jeong, Soo-Hun Hong, Sang-Bom Kang, Myeong-Cheol Kim, Young-Su Chung
  • Publication number: 20150145056
    Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
    Type: Application
    Filed: December 10, 2014
    Publication date: May 28, 2015
    Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
  • Publication number: 20140374840
    Abstract: A semiconductor device includes a substrate and first and second gate electrodes on the substrate. The first gate electrode includes a first gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion and away from the substrate defining a first trench having a first width and a first functional film filling the first trench. The second gate electrode includes a second gate insulation film having a bottom portion on the substrate and sidewall portions extending from the bottom portion defining a second trench having a second width different from the first width, a second functional film conforming to the second gate insulation film in the second trench and defining a third trench, and a metal region in the third trench. The first width may be less than the second width.
    Type: Application
    Filed: June 23, 2014
    Publication date: December 25, 2014
    Inventors: Hye-Lan Lee, Sang-Bom Kang, Jae-Jung Kim, Moon-Kyu Park, Jae-Yeol Song, June-Hee Lee, Yong-Ho Ha, Sang-Jin Hyun
  • Patent number: 8916936
    Abstract: A semiconductor device including: a first gate pattern disposed in a peripheral region of a substrate; a second gate pattern disposed in a cell region of the substrate; a first insulator formed on sidewalls of the first gate pattern; and a second insulator formed on sidewalls of the second gate pattern, wherein a dielectric constant of the first insulator is different from a dielectric constant of the second insulator, and wherein a height of the second insulator is greater than a height of the second gate pattern.
    Type: Grant
    Filed: January 28, 2013
    Date of Patent: December 23, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jung-Chan Lee, Seung-Jae Lee, Sang-Bom Kang, Dae-Young Kwak, Myeong-Cheol Kim, Yong-Ho Jeon
  • Publication number: 20140361313
    Abstract: A method of manufacturing a semiconductor device includes forming first and second gate structures on a substrate in first and second regions, respectively, forming a first capping layer on the substrate by a first high density plasma process, such that the first capping layer covers the first and second gate structures except for sidewalls thereof, removing a portion of the first capping layer in the first region, removing an upper portion of the substrate in the first region using the first gate structure as an etching mask to form a first trench, and forming a first epitaxial layer to fill the first trench.
    Type: Application
    Filed: August 22, 2014
    Publication date: December 11, 2014
    Inventors: Seung-Hun LEE, Byeong-Chan LEE, Sang-Bom KANG
  • Publication number: 20140287564
    Abstract: Semiconductor devices are provided including a substrate having a first surface and a second surface recessed from opposite sides of the first surface, a gate pattern formed on the first surface and having a gate insulating layer and a gate electrode, a carbon-doped silicon buffer layer formed on the second surface, and source and drain regions doped with an n-type dopant or p-type dopant, epitaxially grown on the silicon buffer layer to be elevated from a top surface of the gate insulating layer.
    Type: Application
    Filed: May 27, 2014
    Publication date: September 25, 2014
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Keum-Seok Park, Seung-Hun Lee, Byeong-Chan Lee, Sang-Bom Kang, Hong-Bum Park