Abstract: A planar transformer and a converter including the same include a first core unit including a first receiving portion extending in a first direction; a second core unit spaced from the first core unit, disposed in parallel with the first core unit in a second direction thereof, and including a second receiving portion extending in the first direction; a first coil unit including a first through hole formed in a center portion thereof and a first coil pattern passing through the first receiving portion and the second receiving portion around the first through hole to form a turn; and a second coil unit including a second through hole formed in a center portion thereof and aligned with the first through hole in a third direction thereof, and a second coil pattern passing through the first receiving portion and the second receiving portion around the second through hole.

Abstract: A wafer test system includes a probe card and a test controller. The probe card is connected to at least one device under test (DUT) disposed on a wafer, and is configured to limit a current flowing into the at least one DUT to be about equal to or less than a threshold current. The test controller is configured to control an amplitude of the threshold current.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.

Abstract: A signal detecting circuit of an infrared sensor includes: a cell array in which bolometers sensing infrared rays and outputting signal currents are arranged in an N×M format; a level generator that outputs a plurality of bias voltages corresponding to a plurality of bias levels; N resistor non-uniformity correcting circuits that are located in a column direction of the cell array and supply different bias voltages to each of the bolometers; M resistor non-uniformity correcting circuits that are located in a row direction of the cell array and supply different bias voltages to each of the bolometers; a control unit that sets a bias voltage level of each resistor non-uniformity correcting circuit to correct the resistor non-uniformity of the cell array; and N integrators that integrate the signal currents output from the cell array.

Abstract: Provided is a method of storing configuration data regarding an operating environment of a flash memory device, which includes a memory cell array having an electrical fuse (E-Fuse) block for storing the configuration data. The method includes storing the configuration data in multiple strings of the E-Fuse block, each string including multiple memory cells configured to store one bit.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

Abstract: A probe card transmitting electrical test signals between a tester and a semiconductor device includes a main circuit board configured to receive and transmit electrical signals from the tester, an interface unit electrically connected to the main circuit board, the interface unit including a signal line and a signal connection terminal, and at least one probe unit connected to the interface unit, the probe unit being detachable and including a plurality of probe needles arranged in a pattern corresponding to a pattern of electrode pads of the semiconductor device.

Abstract: A flash memory device includes a memory cell array having a set-up data region configured to store set-up data, wherein the set-up data includes first data and second data. The second data is stored in an empty cell area of the set-up data region. The flash memory also includes a page buffer and decoder configured to read the set-up data from the set-up data region, and a status detector receiving the set-up data from the page buffer and decoder and configured to discriminate the first data from the second data and generate a Pass/Fail status signal.

Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

Abstract: A non-volatile memory device includes a feedback circuit and a precharge switching transistor. The feedback circuit generates a feedback signal based on a voltage level of a bitline during a precharge operation. The precharge switching transistor, in response to the feedback signal, controls a precharge current for precharging the bitline. The speed of the precharge operation may be increased and/or mismatch of the bias signals in precharging a plurality of bitlines may be reduced.

Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

Abstract: A flash memory device includes a chip disable fuse circuit that has a fuse and that outputs a chip disable signal when the fuse is cut out, and a ready/busy control circuit that forcibly activates a ready/busy signal representing an internal operational state in response to the chip disable signal and externally outputs the ready/busy signal through a ready/busy output pin.

Abstract: Disclosed is a flash memory device and a program-verify method. The flash memory device includes; a plurality of memory cells connected between a bit line and a common source line, and a data input/output circuit connected to the bit line and configured to store program data for a selected one of the plurality memory cells. The data input/output circuit maintains the program data during a program-verify operation and controls a voltage level on the bit line in accordance with the program data.

Abstract: A nonvolatile semiconductor memory device includes a string selection transistor coupled to a bit line. The device also includes a plurality of memory cells coupled in series to the string selection transistor, wherein at least one of the memory cells is configured to be in a programmed state during an erase procedure of the plurality of memory cells.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.

Abstract: A nonvolatile memory system is operated by performing a program loop on each of a plurality of memory cells, each program loop comprising at least one program-verify operation and selectively pre-charging bit lines associated with each of the plurality of memory cells during the at least one program-verify operation.

Abstract: A method of programming a nonvolatile memory device comprises applying a program voltage to a selected wordline to program selected memory cells, and performing a verify operation by applying a verify voltage to the selected wordline to determine the programming status of the selected memory cells. The verify operation applies the verify voltage to the selected wordline at least two different times to divide the selected memory cells into at least three regions corresponding to different threshold voltage ranges.