Patents by Inventor Sang-Gyo Chung

Sang-Gyo Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11804549
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: December 16, 2022
    Date of Patent: October 31, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Publication number: 20230121203
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Application
    Filed: December 16, 2022
    Publication date: April 20, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Patent number: 11557677
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: November 23, 2020
    Date of Patent: January 17, 2023
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Publication number: 20210074860
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Application
    Filed: November 23, 2020
    Publication date: March 11, 2021
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung LEE, Yun-seung KANG, Soung-hee LEE, Sang-gyo CHUNG, Hyun-chul LEE
  • Patent number: 10879398
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Grant
    Filed: August 24, 2018
    Date of Patent: December 29, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung Lee, Yun-seung Kang, Soung-hee Lee, Sang-gyo Chung, Hyun-chul Lee
  • Patent number: 10453698
    Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.
    Type: Grant
    Filed: August 22, 2018
    Date of Patent: October 22, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-gyo Chung, Yun-seung Kang, Soung-hee Lee, Ji-seung Lee, Hyun-chul Lee
  • Publication number: 20190221669
    Abstract: An integrated circuit device includes a device isolation trench defining an active area, a gate trench extending in a first direction across the active area and the device isolation film, a gate dielectric film covering an inner wall of the gate trench, and a conductive line filling a part of the gate trench above the gate dielectric film. The active area includes a fin body portion located under the conductive line, and a thinner fin portion protruding from the fin body portion toward the conductive line and having a width less than a width of the fin body portion in the first direction.
    Type: Application
    Filed: August 24, 2018
    Publication date: July 18, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Ji-seung LEE, Yun-seung KANG, Soung-hee LEE, Sang-gyo CHUNG, Hyun-chul LEE
  • Publication number: 20190198339
    Abstract: Methods of fabricating an integrated circuit device are provided. The methods may form feature patterns on a substrate using a quadruple patterning technology (QPT) process including one photolithography process and two double patterning processes. Sacrificial spacers obtained by first double patterning process and spacers obtained by second double patterning process may be formed on a feature layer at an equal level.
    Type: Application
    Filed: August 22, 2018
    Publication date: June 27, 2019
    Inventors: Sang-gyo CHUNG, Yun-seung KANG, Soung-hee LEE, Ji-seung LEE, Hyun-chul LEE
  • Patent number: 9837273
    Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: December 5, 2017
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jong-Sub Lee, Kyoung-Ha Eom, Ha-Neul Lee, Sang-Gyo Chung
  • Publication number: 20170103891
    Abstract: A method of forming fine patterns of semiconductor devices is disclosed. The method comprises forming a hard mask layer on an etch target, which includes first and second regions. The hard mask layer may further have first and second preliminary mask patterns formed on the same. Furthermore, a spacer layer may be formed on the first and second preliminary mask patterns. The spacer layer and the first and second preliminary mask patterns may be partially removed to form first and second spacers on sidewalls of the first and second preliminary mask patterns, respectively. The second spacer in the second region may have a top surface higher than a top surface of the first spacer in the first region. The height differences between the spacers allow forming of first and second patterns in the first and second regions, and thereby forming fine patterns of semiconductor devices.
    Type: Application
    Filed: July 29, 2016
    Publication date: April 13, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Jong-Sub LEE, Kyoung-Ha Eom, Ha-Neul Lee, Sang-Gyo Chung