Patents by Inventor Sang Ho Woo
Sang Ho Woo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10006121Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: GrantFiled: February 25, 2014Date of Patent: June 26, 2018Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Publication number: 20180105951Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber. The cleaning chamber is performed in a batch type with respect to the plurality of substrates.Type: ApplicationFiled: December 14, 2017Publication date: April 19, 2018Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae KIM, Jun-Jin HYON, Sang Ho WOO, Seung Woo SHIN, Hai Won KIM
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Patent number: 9564294Abstract: According to one embodiment of the present invention, a plasma treatment apparatus comprises: a chamber having an inner space in which processes for an object to be treated are performed; and an antenna which is arranged to cover the side part of the chamber, and which forms electric fields in said inner space to generate plasma from the source gas supplied in the inner space. The antenna includes a helical antenna which is formed into a helical shape from one side of the chamber toward the other side of the chamber along a first rotation direction, and which has a current flowing in the first rotation direction; an extension antenna which is connected to one end of the helical antenna positioned at said one side of the chamber, and which has a current flowing in the direction opposite to the first rotation direction; and a connection antenna for interconnecting the extension antenna and the helical antenna.Type: GrantFiled: October 26, 2009Date of Patent: February 7, 2017Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Sang Ho Woo, Il Kwang Yang, Byung Gyu Song
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Patent number: 9425057Abstract: A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.Type: GrantFiled: October 6, 2011Date of Patent: August 23, 2016Assignee: Eugene Technology Co., Ltd.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Patent number: 9396954Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: GrantFiled: October 6, 2011Date of Patent: July 19, 2016Assignee: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Patent number: 8937012Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.Type: GrantFiled: August 30, 2011Date of Patent: January 20, 2015Assignee: Eugene Technology Co., Ltd.Inventors: Hai Won Kim, Sang Ho Woo, Sung Kil Cho, Gil Sun Jang
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Publication number: 20140261186Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: ApplicationFiled: February 25, 2014Publication date: September 18, 2014Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil CHO, Hai Won KIM, Sang Ho WOO, Seung Woo SHIN, Gil Sun JANG, Wan Suk OH
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Patent number: 8828890Abstract: Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method comprises the steps of forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; and forming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber.Type: GrantFiled: August 1, 2011Date of Patent: September 9, 2014Assignee: Eugene Technology Co., Ltd.Inventors: Hai Won Kim, Sang Ho Woo
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Publication number: 20140209024Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, a buffer chamber having a storage space for storing the substrates, and a transfer chamber to which the cleaning chamber, the buffer chamber, and the epitaxial chamber are connected to side surfaces thereof, the transfer chamber comprising a substrate handler for transferring the substrates between the cleaning chamber, the buffer chamber, and the epitaxial chamber. The substrate handler successively transfers the substrates, on which the cleaning process is completed, into the buffer chamber, transfers the substrates stacked within the buffer chamber the epitaxial chamber, and successively transfers the substrates, on which the epitaxial layers are respectively formed, into the buffer chamber.Type: ApplicationFiled: July 31, 2012Publication date: July 31, 2014Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae Kim, Jun Jin Hyon, Sang Ho Woo, Seung Woo Shin, Hai Won Kim
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Publication number: 20140190410Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber.Type: ApplicationFiled: July 31, 2012Publication date: July 10, 2014Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae Kim, Jun Jin Hyon, Sang Ho Woo, Seung Woo Shin, Hai Won Kim
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Publication number: 20140174357Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber. The cleaning chamber is performed in a batch type with respect to the plurality of substrates.Type: ApplicationFiled: July 31, 2012Publication date: June 26, 2014Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae Kim, Jun Jin Hyon, Sang Ho Woo, Seung Woo Shin, Hai Won Kim
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Publication number: 20140144375Abstract: Provided is an equipment for manufacturing a semiconductor. The equipment for manufacturing a semiconductor includes a cleaning chamber in which a cleaning process is performed on substrates, an epitaxial chamber in which an epitaxial process for forming an epitaxial layer on each of the substrates is performed, and a transfer chamber to which the cleaning chamber and the epitaxial chamber are connected to sides surfaces thereof, the transfer chamber including a substrate handler for transferring the substrates, on which the cleaning process is completed, into the epitaxial chamber. The cleaning chamber includes a reaction chamber connected to a side surface of the transfer chamber to perform a reaction process on the substrates and a heating chamber connected to a side surface of the transfer chamber to perform a heating process on the substrates. The reaction chamber and the heating chamber are vertically stacked on each other.Type: ApplicationFiled: July 31, 2012Publication date: May 29, 2014Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Young Dae Kim, Jun Jin Hyon, Sang Ho Woo, Seung Woo Shin
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Publication number: 20130178066Abstract: Provided is a method of manufacturing a memory device having a 3-dimensional structure, which includes alternately stacking one or more dielectric layers and one or more sacrificial layers on a substrate, forming a through hole passing through the dielectric layers and the sacrificial layers, forming a pattern filling the through hole, forming an opening passing through the dielectric layers and the sacrificial layers, and supplying an etchant through the opening to remove the sacrificial layers. The stacking of the dielectric layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, and Si4H10, to deposit a silicon oxide layer. The stacking of the sacrificial layers includes supplying the substrate with one or more gases selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and dichloro silane (SiCl2H2), and ammonia-based gas, to deposit a silicon nitride layer.Type: ApplicationFiled: October 6, 2011Publication date: July 11, 2013Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Publication number: 20130171827Abstract: A method for manufacturing a memory device having a vertical structure according to one embodiment of the present invention comprises: a step for alternatingly laminating one or more insulation layers and one or more sacrificial layers on a substrate; a step for forming a penetration hole for penetrating the insulation layer and the sacrificial layer; a step for forming a pattern for filling up the penetration hole; a step for forming an opening for penetrating the insulation layer and the sacrificial layer; and a step for removing the sacrificial layer by supplying an etchant through the opening, wherein the step for laminating the insulation layer includes a step for depositing a first silicon oxide film by supplying to the substrate at least one gas selected from the group consisting of SiH4, Si2H6, Si3H8, Si4H10, and the step for laminating the sacrificial layer includes a step for depositing a second silicon oxide film by supplying dichlorosilane (SiCl2H2) to the substrate.Type: ApplicationFiled: October 6, 2011Publication date: July 4, 2013Applicant: Eugene Technology Co., Ltd.Inventors: Sung Kil Cho, Hai Won Kim, Sang Ho Woo, Seung Woo Shin, Gil Sun Jang, Wan Suk Oh
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Publication number: 20130130480Abstract: Disclosed is a method for manufacturing a semiconductor device having a multilayer structure. The method for manufacturing a semiconductor device according to the present invention comprises the loading of a substrate into the chamber of a chemical vapor deposition apparatus and the forming of a multilayer structure in which a plurality of doped amorphous silicon layers and a plurality of insulation layers are alternately stacked. Said layers are stacked by alternately and repetitively forming the doped amorphous silicon layer on the substrate by supplying a conductive dopant and silicon precursor into the chamber where the substrate is loaded, and forming the insulation layer containing silicon on the substrate by introducing the silicon precursor and a reaction gas into the chamber where the substrate is loaded.Type: ApplicationFiled: September 1, 2011Publication date: May 23, 2013Applicant: Eugene Technology Co., Ltd.Inventors: Hai Won Kim, Sang Ho Woo, Sung Kill Cho, Gil Sun Jang
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Publication number: 20130130497Abstract: Provided is a production method for a semiconductor device comprising a metal silicide layer. According to one embodiment of the present invention, the production method for a semiconductor device comprises the steps of: forming an insulating layer on a substrate, on which a polysilicon pattern has been formed, in such a way that the polysilicon pattern is exposed; forming a silicon seed layer on the exposed polysilicon pattern that has been selectively exposed with respect to the insulating layer; forming a metal layer on the substrate on which the silicon seed layer has been formed; and forming a metal silicide layer by carrying out a heat treatment on the substrate on which the metal layer has been formed.Type: ApplicationFiled: August 30, 2011Publication date: May 23, 2013Inventors: Hai Won Kim, Sang Ho Woo, Sung Kil Cho, Gil Sun Jang
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Publication number: 20130115783Abstract: Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method comprises the steps of forming a silicon thin film by repeating a silicon deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded and a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber; and forming the insulating film including silicon from the silicon thin film by forming a plasma atmosphere into the chamber.Type: ApplicationFiled: August 1, 2011Publication date: May 9, 2013Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai Won Kim, Sang Ho Woo
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Publication number: 20130101752Abstract: Provided is a method of depositing a cyclic thin film that can provide excellent film properties and step coverage. The method includes the steps of depositing an insulating film by repeatedly performing a deposition step for depositing silicon on a substrate by injecting a silicon precursor into a chamber into which the substrate is loaded, a first purge step for removing a non-reacted silicon precursor and a reacted byproduct from the chamber, a reaction step for forming the deposited silicon as an insulating film including silicon by supplying a first reaction gas into the chamber and a second purge step for removing a non-reacted first reaction gas and a reacted byproduct from the chamber; and densifying the insulating film including silicon by supplying a plasma atmosphere into the chamber.Type: ApplicationFiled: August 1, 2011Publication date: April 25, 2013Applicant: EUGENE TECHNOLOGY CO., LTD.Inventors: Hai Won Kim, Sang Ho Woo
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Patent number: 8295424Abstract: A data receiving apparatus and method includes a current-voltage conversion block, which receives a current-type transmit signal including data and a clock signal inserted into the data at a different level from the data, and then converts the received signal into at least one first voltage and at least one second voltage having a different level from the first voltage, and a comparison block, which makes a comparison between the first and second voltages, and then outputs the received signal as one of the data and the clock signal based on a result of the comparison. The data receiving apparatus can easily recover a clock signal while exhibiting better characteristics during the recovery of the clock signal because it is insensitive to a variation in reference voltage and a variation in current at the transmitting state of the timing controller, which are caused by a process variation.Type: GrantFiled: December 29, 2009Date of Patent: October 23, 2012Assignee: Dongbu HiTek Co., Ltd.Inventors: Woo Jae Choi, Sang Ho Woo, Mi Youn Kim
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Publication number: 20120040520Abstract: Provided is a method of depositing an ultra-fine grain polysilicon thin film. The method includes forming a nitrogen atmosphere in a chamber loaded with a substrate, and supplying a source gas into the chamber to deposit a polysilicon thin film on the substrate, in which the source gas includes a silicon-based gas, a nitrogen-based gas, and a phosphorous-based gas. The forming of the nitrogen atmosphere may include supplying a nitrogen-based gas into the chamber.Type: ApplicationFiled: April 12, 2010Publication date: February 16, 2012Inventors: Hai Won Kim, Sang Ho Woo, Sung Gil Cho