Patents by Inventor Sang-kyun Kim

Sang-kyun Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250036928
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: October 7, 2024
    Publication date: January 30, 2025
    Applicant: Intel Corporation
    Inventors: Arnab Raha, Debabrata Mohapatra, Gautham Chinya, Guruguhanathan Venkataramanan, Sang Kyun Kim, Deepak Mathaikutty, Raymond Sung, Cormac Brick
  • Publication number: 20250030059
    Abstract: An electrode assembly, a battery, and a battery pack and a vehicle including the same are provided. The first electrode of the electrode assembly includes a first active material portion coated with an active material layer along a winding direction and a first uncoated portion not coated with an active material layer and exposed beyond the separator. The first uncoated portion includes a first portion adjacent to the core of the electrode assembly, a second portion adjacent to the outer circumference of the electrode assembly, and a third portion between the first portion and the second portion. The third portion includes a plurality of segments spaced apart along the winding direction by forming a cut groove in plural along the winding axis direction. The height of the first portion may be relatively lower than the height of the uncoated portion at the bottom of the cut groove.
    Type: Application
    Filed: July 20, 2023
    Publication date: January 23, 2025
    Applicant: LG ENERGY SOLUTION, LTD.
    Inventors: Jong-Sik PARK, Jae-Won LIM, Sang-Yeol KIM, Hak-Kyun KIM, Jae-Eun LEE, Je-Jun LEE
  • Publication number: 20250026492
    Abstract: In an assembly system of an aircraft including a fuselage and a wing, the aircraft assembly system may include: a jig unit coupled to the wing to move integrally with the wing; a transfer unit connected to the jig unit and transferring the wing toward the fuselage; a position adjusting unit detachably connected to the jig unit and adjusting a position of the jig unit; and a measuring unit configured for measuring positions of the fuselage and the wing, wherein the fuselage may be relatively fixed to the movement of the wing, wherein the measuring unit may be configured to set a fuselage coordinate system and a wing coordinate system for the fuselage and the wing, respectively, wherein the position adjusting unit may be configured to move the jig unit so that the wing coordinate system coincides with the fuselage coordinate system.
    Type: Application
    Filed: November 30, 2023
    Publication date: January 23, 2025
    Inventors: Dong Ho LEE, Sang Bin HAN, Myung Kyun JEONG, Chang Hoon LEE, Tae Hwan KWAK, Cheol Bae PARK, Jun Young CHOI, Dong Han LEE, Suk Hyun YOON, Jeong Rak KIM
  • Patent number: 12206120
    Abstract: A battery case for a secondary battery according to an embodiment of the present invention can include a cup part having an accommodation space configured to accommodate an electrode assembly in which electrodes and separators are stacked, a sealing part extending to the outside of the cup part, and a gas discharge part which is attached to a hole formed to be punched in at least one of the cup part or the sealing part and through which a gas passes. The gas discharge part can include a melted layer comprising a thermoplastic resin that is melted when heat is applied, and a thermosetting layer laminated on one surface of the melted layer and comprising a thermosetting resin that is not melted by heat.
    Type: Grant
    Filed: August 25, 2020
    Date of Patent: January 21, 2025
    Assignee: LG Energy Solution, Ltd.
    Inventors: Soo Ji Hwang, Yong Su Choi, Sang Hun Kim, Hyung Kyun Yu, Na Yoon Kim
  • Patent number: 12141683
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: November 12, 2024
    Assignee: Intel Corporation
    Inventors: Arnab Raha, Debabrata Mohapatra, Gautham Chinya, Guruguhanathan Venkataramanan, Sang Kyun Kim, Deepak Mathaikutty, Raymond Sung, Cormac Brick
  • Publication number: 20240231839
    Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.
    Type: Application
    Filed: January 18, 2024
    Publication date: July 11, 2024
    Applicant: Intel Corporation
    Inventors: Arnab Raha, Deepak Mathaikutty, Debabrata Mohapatra, Sang Kyun Kim, Gautham Chinya, Cormac Brick
  • Publication number: 20240127488
    Abstract: An image encoding/decoding method, device and recording medium based on accumulation of a region of interest of the present disclosure may include partitioning a current image to acquire a region of interest, cumulatively expressing the region of interest in a reference image of the current image and decoding the current image based on a reference image in which the region of interest is cumulatively expressed.
    Type: Application
    Filed: October 12, 2023
    Publication date: April 18, 2024
    Inventors: Jin Young LEE, Hee Kyung LEE, Sang Kyun KIM
  • Patent number: 11922178
    Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.
    Type: Grant
    Filed: June 25, 2021
    Date of Patent: March 5, 2024
    Assignee: Intel Corporation
    Inventors: Arnab Raha, Deepak Mathaikutty, Debabrata Mohapatra, Sang Kyun Kim, Gautham Chinya, Cormac Brick
  • Publication number: 20230352310
    Abstract: A chemical mechanical polishing method may include polishing a polishing object at a first temperature using a chemical mechanical polishing slurry; and removing the chemical mechanical polishing slurry on the polishing object at a second temperature different from the first temperature. The chemical mechanical polishing slurry may include abrasive particles, a thermoresponsive inhibitor, and deionized water. The thermoresponsive inhibitor may include a thermoresponsive polymer exhibiting a phase-transition between the first temperature and the second temperature. The thermoresponsive polymer may be adsorbed to the hydrophobic layer at the first temperature and desorbed from the hydrophobic layer at the second temperature.
    Type: Application
    Filed: March 27, 2023
    Publication date: November 2, 2023
    Applicant: Samsung Electronics., Ltd.
    Inventors: Yearin Byun, In Kwon Kim, Sang Kyun Kim, Hyo San Lee
  • Patent number: 11702537
    Abstract: A tablet form of an epoxy resin composition for encapsulation of semiconductor elements, where the tablet form of the epoxy resin composition: (i) includes 97 wt % or more of tablets having a diameter of 0.1 mm to less than 2.8 mm and a height of 0.1 mm to less than 2.8 mm, as measured using an ASTM standard sieve; (ii) satisfies the following Equation 1, ? ? ? D × ? ? ? H ? ? ? D + ? ? ? H ? 1.0 , where ?D is a standard deviation of tablet diameters and ?H is a standard deviation of tablet heights, as measured with respect to 50 tablets arbitrarily selected from the tablets; and (iii) the tablets have a compression density of 1.2 g/mL to 1.7 g/mL.
    Type: Grant
    Filed: December 20, 2019
    Date of Patent: July 18, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Sang Jin Kim, Sang Kyun Kim, Tae Shin Eom, Dong Hwan Lee, Young Joon Lee, Yong Han Cho
  • Publication number: 20230211456
    Abstract: A polishing pad for chemical mechanical polishing includes a polymer matrix and a temperature sensitive agent dispersed in the polymer matrix and constituting 1 to 40% by volume of the polishing pad, wherein the temperature sensitive agent includes a two-dimensional (2D) sheet material having a thermal conductivity of 1 W/(m·K) or more.
    Type: Application
    Filed: December 15, 2022
    Publication date: July 6, 2023
    Inventors: Yea Rin Byun, In Kwon Kim, Bo Yun Kim, Sang Kyun Kim, Bo Un Yoon, Hyo San Lee, Byung Keun Hwang
  • Publication number: 20230193080
    Abstract: Slurry compositions for chemical mechanical polishing, chemical mechanical polishing apparatuses using the same, and methods for fabricating a semiconductor device using the same are provided. The slurry composition for chemical mechanical polishing may include polishing particles in an amount of 0.1% to 10% by weight of the slurry composition, an oxidant in an amount of 0.1% to 5% by weight of the slurry composition, a thermo-sensitive agent in an amount of 0.01% to 30% by weight of the slurry composition. The thermo-sensitive agent may include metal nanoparticles or metal oxide nanoparticles, and water, wherein the slurry composition has a pH of 1 to 8.
    Type: Application
    Filed: November 30, 2022
    Publication date: June 22, 2023
    Inventors: YEA RIN BYUN, IN KWON KIM, SANG KYUN KIM, HYO SAN LEE, BYUNG KEUN HWANG
  • Publication number: 20230167566
    Abstract: Cerium oxide nanoparticles and methods of fabricating the same are provided. The cerium oxide nanoparticles may be fabricated by a method that may include injecting metal ions into cerium oxide particles and then removing (e.g., desorbing) at least some of the injected metal ions from the cerium oxide particles.
    Type: Application
    Filed: July 27, 2022
    Publication date: June 1, 2023
    Applicant: Industry-Academic Cooperation Foundation, Yonsei University
    Inventors: IN KWON KIM, Kyu Hyoung Lee, Sang Kyun Kim, Chul Oh Park, Min Young Kim, Hyo San Lee
  • Patent number: 11655363
    Abstract: A tableted epoxy resin composition for encapsulation of semiconductor devices and a semiconductor device encapsulated using the tableted epoxy resin composition, the tableted epoxy resin composition satisfying the following conditions (i) a proportion of tablets of the tableted epoxy resin composition having a diameter of greater than or equal to 0.1 mm and less than 2.8 mm and a height of greater than or equal to 0.1 mm and less than 2.8 mm is about 97 wt % or more, as measured by sieve analysis using ASTM standard sieves; (ii) the tablets have a packed density of greater than about 1.7 g/mL; and (iii) a ratio of packed density to cured density of the tablets is about 0.6 to about 0.87.
    Type: Grant
    Filed: December 18, 2019
    Date of Patent: May 23, 2023
    Assignee: SAMSUNG SDI CO., LTD.
    Inventors: Sang Jin Kim, Sang Kyun Kim, Tae Shin Eom, Dong Hwan Lee, Young Joon Lee, Yong Han Cho
  • Publication number: 20220406051
    Abstract: Disclosed herein are a method and apparatus for distributed image data processing. The method for distributed image data processing includes performing machine learning on an original image to produce a plurality of different task outputs, combining the plurality of task outputs to extract at least one final output, and compressing the final output and transmitting the final output to a server.
    Type: Application
    Filed: June 21, 2022
    Publication date: December 22, 2022
    Applicants: Electronics and Telecommunications Research Institute, Myongji University Industry and Academia Cooperation Foundation
    Inventors: Jin-Young LEE, Hee-Kyung LEE, Sang-Kyun KIM
  • Publication number: 20210326144
    Abstract: Methods, apparatus, systems, and articles of manufacture to load data into an accelerator are disclosed. An example apparatus includes data provider circuitry to load a first section and an additional amount of compressed machine learning parameter data into a processor engine. Processor engine circuitry executes a machine learning operation using the first section of compressed machine learning parameter data. A compressed local data re-user circuitry determines if a second section is present in the additional amount of compressed machine learning parameter data. The processor engine circuitry executes a machine learning operation using the second section when the second section is present in the additional amount of compressed machine learning parameter data.
    Type: Application
    Filed: June 25, 2021
    Publication date: October 21, 2021
    Inventors: Arnab Raha, Deepak Mathaikutty, Debabrata Mohapatra, Sang Kyun Kim, Gautham Chinya, Cormac Brick
  • Publication number: 20210271960
    Abstract: Embodiments of the present disclosure are directed toward techniques and configurations enhancing the performance of hardware (HW) accelerators. Disclosed embodiments include static MAC scaling arrangement, which includes architectures and techniques for scaling the performance per unit of power and performance per area of HW accelerators. Disclosed embodiments also include dynamic MAC scaling arrangement, which includes architectures and techniques for dynamically scaling the number of active multiply-and-accumulate (MAC) within an HW accelerator based on activation and weight sparsity. Other embodiments may be described and/or claimed.
    Type: Application
    Filed: April 30, 2021
    Publication date: September 2, 2021
    Inventors: Arnab Raha, Debabrata Mohapatra, Gautham Chinya, Guruguhanathan Venkataramanan, Sang Kyun Kim, Deepak Mathaikutty, Raymond Sung, Cormac Brick
  • Patent number: 11010166
    Abstract: A processor includes a front end including circuitry to decode a first instruction to set a performance register for an execution unit and a second instruction, and an allocator including circuitry to assign the second instruction to the execution unit to execute the second instruction. The execution unit includes circuitry to select between a normal computation and an accelerated computation based on a mode field of the performance register, perform the selected computation, and select between a normal result associated with the normal computation and an accelerated result associated with the accelerated computation based on the mode field.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: May 18, 2021
    Assignee: Intel Corporation
    Inventors: Debabrata Mohapatra, Perry H. Wang, Xiang Zou, Sang Kyun Kim, Deepak A. Mathaikutty, Gautham N. Chinya
  • Publication number: 20210042617
    Abstract: Systems, apparatuses and methods may provide for technology that identify an assignment of weights of a workload to a plurality of processing elements, where the workload is to be associated with a neural network. The technology generates a representation that is to represent whether each of the weights is a zero value or a non-zero value. The technology further stores the representation into partitions of a storage structure based on the assignment of the weights, where the partitions are each to be dedicated to a different one of the processing elements.
    Type: Application
    Filed: October 27, 2020
    Publication date: February 11, 2021
    Inventors: Gautham Chinya, Deepak Mathaikutty, Guruguhanathan Venkataramanan, Debabrata Mohapatra, Moongon Jung, Sang Kyun Kim, Arnab Raha, Cormac Brick
  • Patent number: D1058623
    Type: Grant
    Filed: June 23, 2023
    Date of Patent: January 21, 2025
    Inventors: Tae Kyun Kim, Nam Seon Lee, Min Seok Oh, Sang Yong Lee, Young Heum Kim