Abstract: A display device according to an embodiment includes a substrate including a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines, and a sub-pixel array structure including a sub-pixel group corresponding to the substrate. The sub-pixel group includes a first sub-pixel, a second sub-pixel in a column different from the first sub-pixel, and third sub-pixels divided in two rows and in two columns with at least one of the first sub-pixel and the second sub-pixel therebetween, wherein the first sub-pixel is in a first column, the second sub-pixel is in a third column, and the third sub-pixels are in second and fourth columns, and wherein a ratio between numbers of the first, second and third sub-pixels is 1:1:4.

Abstract: A display device according to an embodiment includes a substrate including a plurality of gate lines and a plurality of data lines crossing the plurality of gate lines, and a sub-pixel array structure including a sub-pixel group corresponding to the substrate. The sub-pixel group includes a first sub-pixel, a second sub-pixel in a column different from the first sub-pixel, and third sub-pixels divided in two rows and in two columns with at least one of the first sub-pixel and the second sub-pixel therebetween, wherein the first sub-pixel is in a first column, the second sub-pixel is in a third column, and the third sub-pixels are in second and fourth columns, and wherein a ratio between numbers of the first, second and third sub-pixels is 1:1:4.

Abstract: A display device is discussed. The display device according to an embodiment includes a substrate including a plurality of gate lines, and a plurality of data lines crossing the plurality of gate lines; and a sub-pixel array structure including a sub-pixel group corresponding to the substrate. The sub-pixel group includes a first sub-pixel; a second sub-pixel in a column different from the first sub-pixel; and third sub-pixels divided in two rows and in two columns with at least one of the first sub-pixel and the second sub-pixel therebetween.

Abstract: An organic light emitting display device that increases an aperture ratio is provided. The organic light emitting display device comprises a display panel that includes a plurality of sub pixels provided in a pixel region defined by a plurality of scan control lines and a plurality of data lines, each scan control line crossing each data line, wherein some of the plurality of sub pixels have a first aperture ratio, and the other sub pixels have a second aperture ratio smaller than the first aperture ratio.

Abstract: A display device is discussed. The display device according to an embodiment includes a substrate including a plurality of gate lines, and a plurality of data lines crossing the plurality of gate lines; and a sub-pixel array structure including a sub-pixel group corresponding to the substrate. The sub-pixel group includes a first sub-pixel; a second sub-pixel in a column different from the first sub-pixel; and third sub-pixels divided in two rows and in two columns with at least one of the first sub-pixel and the second sub-pixel therebetween.

Abstract: An organic light emitting display device that increases an aperture ratio is provided. The organic light emitting display device comprises a display panel that includes a plurality of sub pixels provided in a pixel region defined by a plurality of scan control lines and a plurality of data lines, each scan control line crossing each data line, wherein some of the plurality of sub pixels have a first aperture ratio, and the other sub pixels have a second aperture ratio smaller than the first aperture ratio.

Abstract: A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.

Abstract: A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.

Abstract: A CMOS latch-type sense amplifying circuit is disclosed. The circuit comprises a CMOS differential amplifier configured to amplify a voltage signal of an input line pair to generate a first amplified voltage signal pair, and provide the first amplified voltage signal pair to an output line pair, a first pre-charge voltage having a first voltage level being applied to the input line pair. The circuit further comprises a CMOS latch-type sense amplifier configured to amplify a voltage signal of the output line pair to generate a second amplified voltage signal pair, and provide the second amplified voltage signal pair to the output line pair. The circuit additionally comprises a first common node controlled by a first common enable signal and connected to both the CMOS differential amplifier and the CMOS latch-type sense amplifier, such that the first common enable signal controls both the CMOS differential amplifier and the CMOS latch-type sense amplifier.

Abstract: A semiconductor memory device including a CMOS-type local sensing amplifier circuit is provided. The semiconductor memory device includes a first input/output (I/O) line pair, a second I/O line pair pre-charged to a one-half power voltage level and receives data from the first I/O line pair, and a pull-up circuit pulling up a voltage of one of the second I/O pair to a full power voltage level.

Abstract: A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip.

Abstract: A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors connected in series, wherein each of the second transistors includes a second gate structure having the pitch. A third transistor and a fourth transistor electrically isolate each of the first and second unit circuits, respectively. An insulation layer covers the first through the fourth transistors. Plugs in the insulation layer are connected to a first gate structure, a second gate structure, a first source region, a first drain region, a second source region or a second drain region. A wiring is connected to the plugs.

Abstract: A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

Abstract: A sense amplifier circuit includes a current sense amplifier, a voltage sense amplifier, and an output stabilizing circuit. The current sense amplifier amplifies differential input currents to generate differential output voltages and provides the differential output voltages to a sense amplifier output line pair. The voltage sense amplifier is coupled to the sense amplifier output line pair to amplify the differential output voltages on the sense amplifier output line pair. The voltage sense amplifier is activated at the time later than a time of activation of the current sense amplifier. The output stabilizing circuit is coupled to the sense amplifier output line pair to stabilize the differential output voltages on the sense amplifier output line pair. The output stabilizing circuit has a positive input resistance. Accordingly, the sense amplifier circuit reduces power consumption and an occupied area on a semiconductor chip.

Abstract: In an embodiment, a sense amplifier can perform a stable differential amplifying operation while having a high differential amplification gain. The sense amplifier comprises a current sense amplification unit, a voltage difference amplification unit, and an output stabilization unit. The current sense amplification unit receives differential input currents and generates differential output voltages corresponding to the differential input currents. The voltage difference amplification unit amplifies a voltage level difference between the differential output voltages through positive feedback using cross-coupled transistors. The output stabilization unit connects output stabilizing elements having a positive input resistance in parallel with the voltage difference amplification unit having a negative input resistance to stabilize the output of the voltage difference amplification unit.

Abstract: A semiconductor device includes first and second unit circuits. Each first unit circuit has first transistors connected in series, wherein each of the first transistors includes a first gate structure having a pitch. Each second unit circuit has second transistors connected in series, wherein each of the second transistors includes a second gate structure having the pitch. A third transistor and a fourth transistor electrically isolate each of the first and second unit circuits, respectively. An insulation layer covers the first through the fourth transistors. Plugs in the insulation layer are connected to a first gate structure, a second gate structure, a first source region, a first drain region, a second source region or a second drain region. A wiring is connected to the plugs.

Abstract: A method of configuring a memory cell array block includes dividing a first unit logic block into sub-array blocks and assigning a portion of the sub-array blocks to a second unit logic block, wherein the memory cell array block corresponds to the portion of the sub-array blocks and the second unit logic block, and the portion of the sub-array blocks and the second unit logic block share a peripheral circuit. The first unit logic block may be divided into the sub-array blocks based on a unit of a word line and/or a unit of a bit line. The peripheral circuit may include a row decoder, a column decoder, a sense amplifier and/or an equalize/precharge circuit. A related addressing method, a memory cell array block and semiconductor memory device are also provided.

Abstract: A memory core includes a first sub-memory array including a plurality of first memory cells, a second sub-memory array including a plurality of second memory cells, a bit line amplification circuit configured to amplify a voltage difference between the first bit line and the second bit line, and a column selection circuit including a first column selection transistor and a second column selection transistor, wherein the first and the second selection transistors share a drain and electrically couple the complementary bit line pair to a complementary local input/output line pair, respectively. As a result, the data error due to the distance mismatching can be reduced.

Abstract: A substrate bonding apparatus for a liquid crystal display device panel includes an upper chamber plate, a lower chamber plate opposing the upper chamber plate, an upper low vacuum chamber provided on the upper chamber plate, a lower low vacuum chamber provided on a rear surface of the lower chamber plate, a sealing member provided on the lower chamber plate, the sealing member projecting from a top surface of the lower chamber plate at a predetermined height to contact the upper chamber plate to form a high vacuum chamber therein, at least two holes provided in each of the upper and lower chamber plates, at least two flow shut-off systems shutting off each of the holes, vacuum pumping system for reducing pressures of the upper and lower low vacuum chambers to low vacuum states, and reducing the high vacuum chamber to a high vacuum state, and upper and lower stages provided to upper and lower chamber plates, respectively, within an inside space of the high vacuum chamber to affix first and second substrates o

Abstract: A temperature detection circuit and method are provided. The temperature detection circuit samples a first delay time for an input signal at a target temperature to be detected, stores a first addresses generated as the sampled result, samples a second delay time for the input address at a present operating temperature, compares a second addresses generated as the sampled result with the first addresses, and generates a detection signal if the target temperature to be detected is the same as the present operating temperature. The temperature detection method is performed by the temperature detection circuit.