Patents by Inventor Sang-Su Kim

Sang-Su Kim has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20200373387
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Application
    Filed: August 14, 2020
    Publication date: November 26, 2020
    Inventors: Jung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
  • Publication number: 20200310443
    Abstract: An apparatus and a method provide a four-dimensional effect to a driver and/or passengers of a vehicle. The apparatus includes a first vehicle controller that analyzes data of content played in an electronic device, sets four-dimensional effect information and generates vehicle control information for realizing the four-dimensional effect according to the set four-dimensional effect information, and a second vehicle controller that performs vehicle control based on the vehicle control information in consideration of a driving status of a vehicle.
    Type: Application
    Filed: September 30, 2019
    Publication date: October 1, 2020
    Inventors: Ki Beom Kwon, Sang Su Kim, Jun Kyung Lee, Jong Yong Nam
  • Patent number: 10663851
    Abstract: The present invention relates to a stereoscopic image display through which after the incident light incident from a projector lens is split into different lights according to polarized components, by selectively delaying the phase of each split light by a predetermined value through an on/off operation of an optical switch module, each light is converted to have the same polarized component, and the synthesized light obtained by synthesizing the lights having the same polarized component is projected on a screen so as to double the luminance on the screen.
    Type: Grant
    Filed: March 17, 2017
    Date of Patent: May 26, 2020
    Inventors: Sang Su Kim, Kim Hung Yu
  • Publication number: 20200135848
    Abstract: A semiconductor device includes a substrate, an active region disposed on the substrate and extending in a first direction, a device isolation layer adjacent to the active region, a gate structure disposed in the active region, the gate structure extending in a second direction crossing the first direction, and covering a portion of the device isolation layer, a gate separation pattern contacting an end of the gate structure, and an impurity region disposed below the gate separation pattern and on the device isolation layer.
    Type: Application
    Filed: May 2, 2019
    Publication date: April 30, 2020
    Inventors: Kangmook Lim, Sang Su Kim, Woo Seok Park, Sung Gi Hur
  • Patent number: 10622444
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Grant
    Filed: September 7, 2018
    Date of Patent: April 14, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
  • Publication number: 20200091286
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Jung-Han LEE, Jae-Hwan LEE, Sang-Su KIM, Hwan-Wook CHOI, Tae-Jong LEE, Seung-Mo HA
  • Patent number: 10566331
    Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.
    Type: Grant
    Filed: January 25, 2019
    Date of Patent: February 18, 2020
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-gil Yang, Sang-su Kim, Sun-wook Kim, Geum-jong Bae, Seung-min Song, Soo-jin Jeong
  • Publication number: 20200051981
    Abstract: A semiconductor device includes: a fin-type active area extending in a first direction protruding from a substrate; a plurality of nanosheet stacked structures; a blocking film covering a part of the upper surface and one sidewall of each of a pair of nanosheet stacked structures adjacent to both sides of the fin-type active area among the plurality of nanosheet stacked structures; a gate electrode extending in a second direction intersecting the first direction on the fin-type active area, the gate electrode including a real gate electrode surrounding the plurality of nanosheets and a dummy gate electrode disposed on the blocking film; and a gate dielectric layer between the real gate electrode and the plurality of nanosheets and between the dummy gate electrode and the blocking film.
    Type: Application
    Filed: January 25, 2019
    Publication date: February 13, 2020
    Inventors: Jung-gil YANG, Sang-su KIM, Sun-wook KIM, Geum-jong BAE, Seung-min SONG, Soo-jin JEONG
  • Patent number: 10411129
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: January 23, 2018
    Date of Patent: September 10, 2019
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park
  • Publication number: 20190227666
    Abstract: A touch screen device and a control method therefor is provided. The touch screen device includes: a touch screen which is mounted on a monitor for displaying an image input from a plurality of image interfaces, on divided screens through a divided screen synthesizer so as to receive an input touch state; a touch control unit for selecting a matching touch interface from among a plurality of touch interfaces on the basis of division information of divided screens with respect to touch coordinates input from the touch screen, and converting the touch coordinates into absolute coordinates for the matching touch interface; and a touch output unit for outputting absolute coordinates to a matching touch interface by the touch control unit.
    Type: Application
    Filed: August 9, 2017
    Publication date: July 25, 2019
    Inventors: Son Ou LEE, Sang Su KIM, Tae Heon NOH, Hyeoung Kyu CHANG, IL GOOK CHO, Woo HWANGBO
  • Publication number: 20190107728
    Abstract: The present invention relates to a stereoscopic image display through which after the incident light incident from a projector lens is split into different lights according to polarized components, by selectively delaying the phase of each split light by a predetermined value through an on/off operation of an optical switch module, each light is converted to have the same polarized component, and the synthesized light obtained by synthesizing the lights having the same polarized component is projected on a screen so as to double the luminance on the screen.
    Type: Application
    Filed: March 17, 2017
    Publication date: April 11, 2019
    Inventors: Kim Hung YU, Sang Su KIM
  • Publication number: 20190019864
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Application
    Filed: September 7, 2018
    Publication date: January 17, 2019
    Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
  • Patent number: 10165415
    Abstract: A method for performing geomagnetic signal processing using a geomagnetic signal processing apparatus is provided. The method includes obtaining a geomagnetic signal based on a geomagnetic sensor output; converting the obtained geomagnetic signal into a high frequency signal having a frequency equal to or higher than a reference frequency using a signal processing filter; extracting abnormal high frequency signal values outside a predetermined critical range from the converted high frequency signal; determining whether a sum of the extracted abnormal high frequency signal values converges into a critical range a preset time window; and correcting the geomagnetic signal based on the determining.
    Type: Grant
    Filed: October 17, 2017
    Date of Patent: December 25, 2018
    Assignee: SAMSUNG SDS CO., LTD.
    Inventors: Sang Su Kim, Young Wn Kwun, Jung Woo Cho, Ho Jun Lee, Young Mi Son
  • Patent number: 10137533
    Abstract: A multi-functional apparatus for testing and etching a substrate capable of increasing spatial efficiency and manufacturing efficiency by performing testing and etching operations in a same chamber body and a substrate processing apparatus including the same, the multi-functional apparatus including a chamber body having an entrance into which the substrate is injected in one of its sides and an exit from which the substrate is ejected in another one of its sides; a transfer unit disposed inside of the chamber body and for transferring the injected substrate in a direction from the entrance to the exit; a laser etching unit disposed on an upper portion of the transfer unit and for etching a part of the substrate disposed on the transfer unit; and a testing unit for testing the substrate disposed on the transfer unit.
    Type: Grant
    Filed: May 16, 2016
    Date of Patent: November 27, 2018
    Assignee: Samsung Display Co., Ltd.
    Inventors: Sung-Hwan Kim, Sang-Su Kim, Byoung-Seong Jeong, Je-Hyun Song, Tae-Hun Lee, Sung-Won Yang, Tae-Hyung Kim
  • Patent number: 10074717
    Abstract: A semiconductor device includes a plurality of active fins defined by an isolation layer on a substrate, a gate structure on the active fins and the isolation layer, and a gate spacer structure covering a sidewall of the gate structure. A sidewall of the gate structure includes first, second, and third regions having first, second, and third slopes, respectively. The second slope increases from a bottom toward a top of the second region. The second slope has a value at the bottom of the second region less than the first slope. The third slope is greater than the second slope.
    Type: Grant
    Filed: January 12, 2016
    Date of Patent: September 11, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Han Lee, Jae-Hwan Lee, Sang-Su Kim, Hwan-Wook Choi, Tae-Jong Lee, Seung-Mo Ha
  • Publication number: 20180151736
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Application
    Filed: January 23, 2018
    Publication date: May 31, 2018
    Inventors: Shigenobu Maeda, Tae-Yong KWON, Sang-Su KIM, Jae-Hoo PARK
  • Patent number: 9984925
    Abstract: A semiconductor device, including a first fin-type pattern; a first gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and including an upper portion and a lower portion; a second gate spacer on the first fin-type pattern, intersecting the first fin-type pattern, and being spaced apart from the first gate spacer; a first trench defined by the first gate spacer and the second gate spacer; a first gate electrode partially filling the first trench; a first capping pattern on the first gate electrode and filling the first trench; and an interlayer insulating layer covering an upper surface of the capping pattern, a width of the upper portion of the first gate spacer decreasing as a distance from an upper surface of the first fin-type pattern increases, and an outer sidewall of the upper portion of the first gate spacer contacting the interlayer insulating layer.
    Type: Grant
    Filed: June 14, 2016
    Date of Patent: May 29, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yong-Ho Jeon, Sang-Su Kim, Cheol Kim, Yong-Suk Tak, Myung-Geun Song, Gi-Gwan Park
  • Patent number: 9978835
    Abstract: A semiconductor device includes at least one nanowire that is disposed over a substrate, extends to be spaced apart from the substrate, and includes a channel region, a gate that surrounds at least a part of the channel region, and a gate dielectric film that is disposed between the channel region and the gate. A source/drain region that contacts one end of the at least one nanowire is formed in a semiconductor layer that extends from the substrate to the one end of the at least one nanowire. Insulating spacers are formed between the substrate and the at least one nanowire. The insulating spacers are disposed between the gate and the source/drain region and are formed of a material that is different from a material of the gate dielectric film.
    Type: Grant
    Filed: October 31, 2016
    Date of Patent: May 22, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jung-Gil Yang, Sang-Su Kim, Sung-Gi Hur
  • Publication number: 20180115874
    Abstract: A method for performing geomagnetic signal processing using a geomagnetic signal processing apparatus is provided. The method includes obtaining a geomagnetic signal based on a geomagnetic sensor output; converting the obtained geomagnetic signal into a high frequency signal having a frequency equal to or higher than a reference frequency using a signal processing filter; extracting abnormal high frequency signal values outside a predetermined critical range from the converted high frequency signal; determining whether a sum of the extracted abnormal high frequency signal values converges into a critical range a preset time window; and correcting the geomagnetic signal based on the determining.
    Type: Application
    Filed: October 17, 2017
    Publication date: April 26, 2018
    Applicant: SAMSUNG SDS CO., LTD.
    Inventors: Sang Su KIM, Young Wn KWUN, Jung Woo CHO, Ho Jun LEE, Young Mi SON
  • Patent number: 9893186
    Abstract: Methods of forming a semiconductor device may include forming a fin-type active pattern that extends in a first direction on a substrate, the fin-type active pattern including a lower pattern on the substrate and an upper pattern on the lower pattern. A field insulating layer is formed on the substrate, the sidewalls of the fin-type active pattern, and a portion upper pattern protruding further away from the substrate than a top surface of the field insulating layer. A dummy gate pattern that intersects the fin-type active pattern and that extends in a second direction that is different from the first direction is formed. The methods include forming dummy gate spacers on side walls of the dummy gate pattern, forming recesses in the fin-type active pattern on both sides of the dummy gate pattern and forming source and drain regions on both sides of the dummy gate pattern.
    Type: Grant
    Filed: July 29, 2016
    Date of Patent: February 13, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Shigenobu Maeda, Tae-Yong Kwon, Sang-Su Kim, Jae-Hoo Park