Abstract: A neuromorphic device includes a synapse. The synapse, according to an embodiment, includes a first electrode, a second electrode spaced apart from the first electrode, an oxygen-containing layer disposed between the first electrode and the second electrode, the oxygen-containing layer including oxygen ions, and a reactive metal layer disposed between the oxygen-containing layer and the second electrode. The oxygen-containing layer includes oxygen ions. The reactive metal layer is capable of reacting with the oxygen ions of the oxygen-containing layer. A width of the reactive metal layer decreases along a direction toward the oxygen-containing layer from the second electrode.

Abstract: A synapse and a neuromorphic device including the same are provided. The synapse includes: a first electrode; a second electrode spaced apart from the first electrode; an oxygen-containing layer disposed between the first electrode and the second electrode; a reactive metal layer disposed between the oxygen-containing layer and the second electrode and capable of reacting with oxygen ions from the oxygen-containing layer; and an oxygen diffusion-retarding layer provided between the oxygen-containing layer and the reactive metal layer, the oxygen diffusion-retarding layer hindering movement of oxygen ions from the oxygen-containing layer to the reactive metal layer.

Abstract: The present invention relates to a pattern recognition method and a pattern recognition apparatus for the same. According to the present invention, a pattern recognition method comprises: receiving data of a recognition object having a pattern; and recognizing the pattern using an electronic device having a synapse characteristic including a plurality of RRAMs (Resistance Random Access Memories), wherein each RRAM includes a variable resistance layer and has multiple memory states depending on variations in resistance of the variable resistance layer.

Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

Abstract: A frequency tuning apparatus may include an oscillator and a memory element connected to the oscillator. The memory element may have a variable resistance. An oscillation frequency of the oscillator may vary according to a resistance state of the memory element. The oscillator may be a ring oscillator. The memory element may be connected to an input terminal or a power terminal of the oscillator.

Abstract: A variable resistive memory device includes a substrate comprising a cell region and a peripheral region, a word line extending in a first direction formed on the substrate of the cell region, a switching element formed on the word line, a variable resistance layer formed on the word line, and at least one transistor comprising a gate stack, the gate stack formed on the substrate of the peripheral region, wherein the word line comprises a metal layer formed at a same level as the gate stack.

Abstract: An apparatus and method for converting data between a floating-point number and an integer is provided. The apparatus includes a data converter configured to determine a sign of input binary data and an output format to which to convert the input binary data and convert the input binary data into a one's complement number based on the sign and the output format of the input binary data, a bias value generator configured to determine whether the input binary data has been rounded up based on a rounding mode of the input binary data and generate a bias value accordingly; and an adder configured to convert the input binary data into a two's complement number by adding the one's complement number and the bias value.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.

Abstract: Provided are a semiconductor device and a method of forming the semiconductor device. The method may include forming a semiconductor pattern on a substrate, forming an interlayer insulating layer including an opening exposing the semiconductor pattern, forming a semiconductor ohmic pattern on the semiconductor pattern, forming an electrode ohmic layer on the semiconductor ohmic pattern, performing a wet etching on the electrode ohmic layer, and forming an electrode pattern on the etched electrode ohmic layer.

Abstract: A non-volatile memory device includes a semiconductor substrate, first and second control gates, and first and second charge storage patterns. The semiconductor substrate includes a protruding active pin having a source region, a drain region and a channel region located between the source and drain regions. The first control gate is located on a first sidewall of the channel region, and the second control gate is located on a second sidewall of the channel region. The second control gate is separated from the first control gate. The first charge storage pattern is located between the first sidewall and the first control gate, and the second charge storage pattern is located between the second sidewall and the second control gate.