Patents by Inventor Sang Won Park

Sang Won Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10699782
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: July 3, 2019
    Date of Patent: June 30, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Publication number: 20200168547
    Abstract: A three-dimensional semiconductor memory device may include a first stack structure block including first stack structures arranged in a first direction on a substrate, a second stack structure block including second stack structures arranged in the first direction on the substrate, a separation structure disposed on the substrate between the first and second stack structure blocks and including first mold layers and second mold layers, and a contact plug penetrating the separation structure. A bottom surface of the contact plug may contact the substrate.
    Type: Application
    Filed: October 4, 2019
    Publication date: May 28, 2020
    Inventors: BONGSOON LIM, SANG-WAN NAM, SANG-WON PARK, SANG-WON SHIM, HONGSOO JEON, YONGHYUK CHOI
  • Patent number: 10658040
    Abstract: A storage device includes a nonvolatile memory device and a controller. The controller provides the nonvolatile memory device with first data, an address, and a program start command and provides the nonvolatile memory device with second data after the program start command is provided the nonvolatile memory device. The nonvolatile memory device is configured to initiate a program operation, which is based on the first data, in response to the program start command and to continue to perform, based on the first data and the second data, the program operation when the second data is provided to the nonvolatile memory device. The nonvolatile memory device is configured to perform a program and a verification read of a first program loop based on the first data, the verification read of the first program loop being performed using one verification voltage.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: May 19, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Bongsoon Lim, Jung-Yun Yun, Ji-Suk Kim, Sang-Won Park
  • Publication number: 20200135758
    Abstract: A nonvolatile memory device includes a semiconductor substrate including a page buffer region, a memory cell array, bitlines, first vertical conduction paths, and second vertical conduction paths. The memory cell array is formed in a memory cell region above the semiconductor substrate and includes memory cells. The bitlines extend in a column direction above the memory cell array. Each of bitlines is cut into each of first bitline segments and each of second bitline segments. The first vertical conduction paths extend in a vertical direction and penetrate a column-directional central region of the memory cell region. The first vertical conduction paths connect the first bitline segments and the page buffer region. The second vertical conduction paths extend in the vertical direction and penetrate the column-directional central region. The second vertical conduction paths connect the second bitline segments and the page buffer region.
    Type: Application
    Filed: June 13, 2019
    Publication date: April 30, 2020
    Inventors: Sang-Won PARK, Sang-Wan NAM, Bong-Soon LIM
  • Publication number: 20200126980
    Abstract: Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.
    Type: Application
    Filed: March 5, 2017
    Publication date: April 23, 2020
    Applicant: Intel Corporation
    Inventors: Sang-Won Park, Dennis G. Hanken, Sishir Bhowmick, Leonard C. Pipes
  • Patent number: 10622091
    Abstract: A nonvolatile memory device includes a memory cell array and a bad block remapping circuit. The memory cell array includes a first mat and a second mat that are paired with each other. The first mat includes a plurality of first memory blocks. The second mat includes a plurality of second memory blocks. A first selection memory block among the plurality of first memory blocks and a second selection memory block among the plurality of second memory blocks are accessed based on a first address. The bad block remapping circuit generates a first remapping address based on the first address when it is determined that the first selection memory block is defective. A first remapping memory block among the plurality of first memory blocks and the second selection memory block are accessed based on the first remapping address.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: April 14, 2020
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jun Lee, Bong-Soon Lim, Sang-Won Park
  • Patent number: 10604894
    Abstract: The present invention provides a method of carbonating carbon dioxide with high purity using a paper mill waste sludge by preparing a paper mill waste sludge which is a waste product discharged during the production of papermaking, adding acid to the paper mill waste sludge and reacting the acid therewith to produce a mixed solution and stirring, separating a supernatant of the mixed solution into an eluate, adding a basic substance to the eluate and adjusting pH to precipitate some of the ions in the eluate, and then adding a reaction initiator to the eluate in which some ions are precipitated and removed, and injecting carbon dioxide for a carbonation reaction.
    Type: Grant
    Filed: November 9, 2017
    Date of Patent: March 31, 2020
    Assignee: Korea Institute of Geoscience and Mineral Resources
    Inventors: Chi-Wan Jeon, Sang-Won Park, Jun-Hwan Bang, Kyung-Sun Song, Seung-Woo Lee, Hwan-Ju Jo
  • Patent number: 10538663
    Abstract: The present disclosure relates to a phosphorus compound represented by the following Chemical Formula 1. In the above Chemical Formula 1, Ar is aryl and R1, R2, R3, R4, R5, and R6 are each independently H, substitutable linear or branched C1-C20 alkyl and substitutable C6-C20 aryl, the aryl includes a member selected from the group consisting of phenyl, biphenyl, naphthalene, fluorene, anthracene, phenanthrene, pyrene, fluoranthen, chrysene, benzofluoranthen, perylene, quinoline, indenoanthracene, indenophenanthrene, hydroanthracene, dibenzothiophen, dibenzofuran, and combinations thereof, and the substitution is substitution with C1-C6 alkyl or C6-C20 aryl, but may not be limited thereto.
    Type: Grant
    Filed: August 21, 2018
    Date of Patent: January 21, 2020
    Assignee: Research & Business Foundation Sungkyunkwan University
    Inventors: Jinhwan Kim, Soo-Jung Kang, Vo Thi Hai, Sang-Won Park
  • Patent number: 10490280
    Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.
    Type: Grant
    Filed: June 14, 2019
    Date of Patent: November 26, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyo Shim, Sang-won Park, Su-chang Jeon
  • Publication number: 20190325952
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Application
    Filed: July 3, 2019
    Publication date: October 24, 2019
    Inventors: SANG-WON PARK, DONGKYO SHIM, KITAE PARK, SANG-WON SHIM
  • Publication number: 20190295651
    Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.
    Type: Application
    Filed: June 14, 2019
    Publication date: September 26, 2019
    Inventors: Dong-kyo Shim, Sang-won Park, Su-chang Jeon
  • Patent number: 10395741
    Abstract: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
    Type: Grant
    Filed: September 24, 2018
    Date of Patent: August 27, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Su-Chang Jeon, Dong-Kyo Shim
  • Patent number: 10388367
    Abstract: A nonvolatile memory device includes a voltage generator that sequentially provides a first setup voltage and second setup voltage to a word line of a memory cell array, and control logic including a time control unit that determines a word line setup time for the word line in relation to the second setup voltage based on a difference between the first and second setup voltages.
    Type: Grant
    Filed: November 15, 2016
    Date of Patent: August 20, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Dongkyo Shim, Kitae Park, Sang-Won Shim
  • Patent number: 10382993
    Abstract: The present disclosure relates to a 5G or pre-5G communication system that will be provided to support a higher data transmission rate beyond a 4G communication system such as LTE. Disclosed is an interference measurement method and device in a flexible duplex system. The method comprises the steps of: determining whether uplink (UL) grant for allocating UL transmission has been received from a base station in a first subframe; when the UL grant has not been received, measuring inter-cell interference for an uplink interference measurement resource (IMR) in at least one second subframe determined by the first subframe; and when the UL grant has been received, measuring inter-cell interference for the uplink interference measurement resource (IMR) in at least one third subframe before a subframe that is indicated by the UL grant.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: August 13, 2019
    Assignees: Samsung Electronics Co., Ltd., Yonsei University—Industry Foundation
    Inventors: Hyoung-Ju Ji, Sang-Won Park, Youn-Sun Kim, Chung-Yong Lee, Sang-Geun Lee
  • Patent number: 10325657
    Abstract: Methods of programming a non-volatile memory device including N string selection lines, a word line, first and second bit line groups are provided. The method may include sequentially programming first memory cells that are connected to the word line and at least one bit line included in the first bit line group by sequentially selecting the N string selection lines in response to sequentially applied first to N-th addresses, and then sequentially programming second memory cells that are connected to the word line and at least one bit line included in the second bit line group by sequentially selecting one of the N string selection lines in response to sequentially applied N+1-th to 2N-th addresses.
    Type: Grant
    Filed: October 25, 2017
    Date of Patent: June 18, 2019
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Dong-kyo Shim, Sang-won Park, Su-chang Jeon
  • Publication number: 20190114099
    Abstract: A non-volatile memory device having a memory chip is provided. The memory chip having a memory cell array including a plurality of memory planes sharing a pad, the pad configured to communicate input and output signals. The memory chip also having a control circuit configured to monitor operations of the plurality of memory planes, and control an operation of at least one of the plurality of memory planes based on a result of the monitoring such that peak power intervals of the plurality of memory planes are at least partially distributed.
    Type: Application
    Filed: September 28, 2018
    Publication date: April 18, 2019
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Su-chang JEON, Sang-won Park, Dong-kyo Shim, Dong-hun Kwak
  • Publication number: 20190071566
    Abstract: The present disclosure relates to a phosphorus compound represented by the following Chemical Formula 1. In the above Chemical Formula 1, Ar is aryl and R1, R2, R3, R4, R5, and R6 are each independently H, substitutable linear or branched C1-C20 alkyl and substitutable C6-C20 aryl, the aryl includes a member selected from the group consisting of phenyl, biphenyl, naphthalene, fluorene, anthracene, phenanthrene, pyrene, fluoranthen, chrysene, benzofluoranthen, perylene, quinoline, indenoanthracene, indenophenanthrene, hydroanthracene, dibenzothiophen, dibenzofuran, and combinations thereof, and the substitution is substitution with C1-C6 alkyl or C6-C20 aryl, but may not be limited thereto.
    Type: Application
    Filed: August 21, 2018
    Publication date: March 7, 2019
    Applicant: RESEARCH & BUSINESS FOUNDATION SUNGKYUNKWAN UNIVERSITY
    Inventors: Jinhwan KIM, Soo-Jung KANG, Vo Thi HAI, Sang-Won PARK
  • Publication number: 20190035471
    Abstract: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
    Type: Application
    Filed: September 24, 2018
    Publication date: January 31, 2019
    Inventors: SANG-WON PARK, SU-CHANG JEON, DONG-KYO SHIM
  • Patent number: 10147634
    Abstract: Techniques are disclosed for providing trench isolation of semiconductive fins using flowable dielectric materials. In accordance with some embodiments, a flowable dielectric can be deposited over a fin-patterned semiconductive substrate, for example, using a flowable chemical vapor deposition (FCVD) process. The flowable dielectric may be flowed into the trenches between neighboring fins, where it can be cured in situ, thereby forming a dielectric layer over the substrate, in accordance with some embodiments. Through curing, the flowable dielectric can be converted, for example, to an oxide, a nitride, and/or a carbide, as desired for a given target application or end-use. In some embodiments, the resultant dielectric layer may be substantially defect-free, exhibiting no or an otherwise reduced quantity of seams/voids.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 4, 2018
    Assignee: INTEL CORPORATION
    Inventors: Ritesh Jhaveri, Jeanne L. Luce, Sang-Won Park, Dennis G. Hanken
  • Patent number: 10102909
    Abstract: A nonvolatile memory device includes a cell string having a plurality of memory cells connected to one bit line. A page buffer is connected to the bit line via a sensing node and connected to the cell string via the bit line. The page buffer includes a first latch for storing bit line setup information and a second latch for storing forcing information. The first latch is configured to output the bit line setup information to the sensing node, and the second latch is configured to output the forcing information to the sensing node independently of the first latch.
    Type: Grant
    Filed: April 11, 2017
    Date of Patent: October 16, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Sang-Won Park, Su-Chang Jeon, Dong-Kyo Shim