Patents by Inventor Sangki Hong

Sangki Hong has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8222121
    Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: July 17, 2012
    Assignee: Tezzaron Semiconductor, Inc.
    Inventors: Robert Patti, Sangki Hong, Chockalingam Ramasamy
  • Patent number: 8183127
    Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
    Type: Grant
    Filed: May 24, 2010
    Date of Patent: May 22, 2012
    Assignee: Tezzaron Semiconductor, Inc.
    Inventors: Robert Patti, Sangki Hong, Ramasamy Chockalingam
  • Publication number: 20110117701
    Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
    Type: Application
    Filed: January 11, 2011
    Publication date: May 19, 2011
    Inventors: Robert Patti, Sangki Hong, Chockalingam Ramasamy
  • Patent number: 7898095
    Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial stepper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
    Type: Grant
    Filed: March 20, 2006
    Date of Patent: March 1, 2011
    Assignee: Tezzaron Semiconductor, Inc.
    Inventors: Robert Patti, Sangki Hong, Chockalingam Ramasamy
  • Publication number: 20100233850
    Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
    Type: Application
    Filed: May 24, 2010
    Publication date: September 16, 2010
    Inventors: Robert Patti, Sangki Hong, Ramasamy Chockalingam
  • Patent number: 7750488
    Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
    Type: Grant
    Filed: July 10, 2006
    Date of Patent: July 6, 2010
    Assignee: Tezzaron Semiconductor, Inc.
    Inventors: Robert Patti, Sangki Hong, Ramasamy Chockalingam
  • Publication number: 20080006938
    Abstract: A basic building block for wafer scale stacked integrated circuits is disclosed. The building block includes an integrated circuit device having an integrated circuit substrate having a circuit layer sandwiched between a buffer layer and a dielectric layer. The dielectric layer has a top side and a bottom side, the bottom side being in contact with the circuit layer. The top surface of the dielectric layer includes a plurality of pads. Each pad extends above the top surface by a predetermined distance. The pads have dimensions that reduce irregularities in the top surface of the pads. In addition, the pads are arranged in a manner to promote planarization of the surface of the wafer via CMP.
    Type: Application
    Filed: July 10, 2006
    Publication date: January 10, 2008
    Inventors: Robert Patti, Sangki Hong, Ramasamy Chockalingam
  • Publication number: 20070216041
    Abstract: A method for stacking integrated circuit substrates and the substrates used therein are disclosed. In the method, an integrated circuit substrate having top and bottom surfaces is provided. The substrate is divided vertically into a plurality of layers including an integrated circuit layer having integrated circuit elements constructed therein and a buffer layer adjacent to the bottom surface. An alignment fiducial mark extending from the top surface of the wafer into the substrate to a depth below that of the circuit layer is constructed. The vias are arranged in a pattern that provides a fiducial mark when viewed from the bottom surface of the substrate. The pattern can be chosen such that it is recognized by a commercial steeper/scanner/contact mask aligner when viewed from said backside of said wafer. After the substrate is thinned, the alignment fiducial mark is then used to position a mask used in subsequent processing.
    Type: Application
    Filed: March 20, 2006
    Publication date: September 20, 2007
    Inventors: Robert Patti, Sangki Hong, Chockalingam Ramasamy
  • Publication number: 20050224921
    Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.
    Type: Application
    Filed: June 9, 2005
    Publication date: October 13, 2005
    Inventors: Subhash Gupta, Paul Ho, Sangki Hong
  • Patent number: 6566260
    Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: May 20, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Patent number: 6531390
    Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: March 11, 2003
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Patent number: 6489233
    Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: December 3, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Publication number: 20020163072
    Abstract: An integrated circuit wafer element and an improved method for bonding the same to produce a stacked integrated circuit. An integrated circuit wafer according to the present invention includes a substrate having first and second surfaces constructed from a wafer material, the first surface having a circuit layer that includes integrated circuit elements constructed thereon. A plurality of vias extend from the first surface through the circuit layer and terminate in the substrate at a first distance from the first surface. The vias include a stop layer located in the bottom of each via constructed from a stop material that is more resistant to chemical/mechanical polishing (CMP) than the wafer material. The vias may be filled with an electrically conducting material to provide vertical connections between the various circuit layers in a stacked integrated circuit.
    Type: Application
    Filed: May 1, 2001
    Publication date: November 7, 2002
    Inventors: Subhash Gupta, Paul Kwok Keung Ho, Sangki Hong
  • Publication number: 20020155693
    Abstract: A new method of fabricating self-aligned, anti-via interconnects has been achieved. A semiconductor substrate is provided. A metal layer is deposited overlying the semiconductor substrate. The metal layer may comprise a composite stack of two metal layers. The metal layers may additionally be separated by an etch stopping layer. An anti-reflective coating layer is deposited overlying the metal layer. The metal layer is etched through to form connective lines. The metal layer is then etched partially through to form vias. The partial etching through may be accomplished by timed etching or by use of the optional etching stop layer. A dielectric layer is deposited overlying the vias, the connective lines and the semiconductor substrate. The dielectric layer may comprise a low-k material. The dielectric layer is polished down to complete the self-aligned, anti-via interconnects in the manufacture of the integrated circuit device.
    Type: Application
    Filed: April 23, 2001
    Publication date: October 24, 2002
    Applicant: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Sangki Hong, Subhash Gupta, Kwok Keung Paul Ho
  • Patent number: 6429122
    Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Grant
    Filed: August 10, 2001
    Date of Patent: August 6, 2002
    Assignee: Chartered Semiconductor Manufacturing, Ltd
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Patent number: 6376353
    Abstract: Improved processes for fabricating wire bond pads on pure copper damascene are disclosed by this invention. The invention relates to various methods of fabrication used for semiconductor integrated circuit devices, and more specifically to the formation of Al—Cu alloy top pad metal layers are described, which improve adhesion among the wire bond, top Al—Cu and the underlying copper pad metallurgy. This invention describes processes wherein a special Al—Cu bond layer or region is placed on top of the underlying copper pad metal. This Al—Cu bond pad on pure copper (with barrier layer in-between) provides for improved wire bond adhesion to the bond pad and prevents peeling during wire bond adhesion tests.
    Type: Grant
    Filed: July 3, 2000
    Date of Patent: April 23, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Mei Sheng Zhou, Sangki Hong, Simon Chooi
  • Patent number: 6372636
    Abstract: A method of forming amorphous silicon spacers followed by the forming of metal nitride over the spacers in a copper damascene structure -single, dual, or multi-structure- is disclosed in order to prevent the formation of fluorides in copper. In a first embodiment, the interconnection between the copper damascene and an underlying copper metal layer is made by forming an opening from the dual damascene structure to the underlying copper layer after the formation of the metal nitride layer over the amorphous silicon spacers formed on the inside walls of the dual damascene structure. In the second embodiment, the interconnection between the dual damascene structure and the underlying copper line is made from the dual damascene structure by etching into the underlying copper layer after the forming of the amorphous silicon spacers and before the forming of the metal nitride layer.
    Type: Grant
    Filed: June 5, 2000
    Date of Patent: April 16, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Patent number: 6352917
    Abstract: A new method of forming metal interconnect levels containing damascene interconnects and via plugs in the manufacture of an integrated circuit device has been achieved. The method creates a reversed dual damascene structure. A first dielectric layer is provided overlying a semiconductor substrate. The dielectric layer is patterned to form trenches for planned damascene interconnects. Insulating spacers may optionally be formed on the trench sidewalls. A conductive barrier layer is deposited overlying the dielectric layer and lining the trenches. A metal layer, preferably comprising copper, is deposited overlying the conductive barrier layer and filling the trenches. The metal layer and the conductive barrier layer are polished down to thereby form the damascene interconnects. A passivation layer may optionally be deposited. The damascene interconnects are patterned to form via plugs overlying the damascene interconnects.
    Type: Grant
    Filed: June 21, 2000
    Date of Patent: March 5, 2002
    Assignee: Chartered Semiconductor Manufacturing Ltd.
    Inventors: Subhash Gupta, Mei-Sheng Zhou, Simon Chooi, Sangki Hong
  • Publication number: 20020001952
    Abstract: A method for forming dual-damascene type conducting interconnects with nonmetallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Application
    Filed: August 10, 2001
    Publication date: January 3, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong
  • Publication number: 20020001951
    Abstract: A method for forming dual-damascene type conducting interconnects with non-metallic barriers that protect said interconnects from fluorine out-diffusion from surrounding low-k, fluorinated dielectric materials. One embodiment of the method is particularly suited for forming such interconnects in microelectronics fabrications of the sub 0.15 micron generation.
    Type: Application
    Filed: August 10, 2001
    Publication date: January 3, 2002
    Applicant: CHARTERED SEMICONDUCTOR MANUFACTURING LTD.
    Inventors: Simon Chooi, Subhash Gupta, Mei-Sheng Zhou, Sangki Hong