Patents by Inventor Sanjay A. Desai

Sanjay A. Desai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Testable RAM architecture in a microprocessor having embedded cache memory
    Patent number: 5249281
    Abstract: A microprocessor with embedded cache memory is disclosed. In a "test mode" of operation, caches are accessed directly from the memory interface signals. Direct writing and reading to/from the instruction and data caches allows the testing of the functionality of the cache memory arrays. External memory interface is granted to an external master via a bus arbitration mechanism so that the test mode operation can be utilized.
    Type: Grant
    Filed: October 12, 1990
    Date of Patent: September 28, 1993
    Assignee: LSI Logic Corporation
    Inventors: Michael Fuccio, Sanjay Desai