Patents by Inventor Santiago Iriarte
Santiago Iriarte has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20140266140Abstract: A voltage generator is provided which is reliable, self starting and only requires a few components. The voltage generator comprises a first stage that provides a current to a second stage. The first stage has a temperature coefficient of one sign, such as positive, and the second stage has an opposing temperature coefficient, e.g. negative. The responses are summed such that the overall temperature coefficient is reduced.Type: ApplicationFiled: March 11, 2014Publication date: September 18, 2014Applicant: Analog Devices TechnologyInventors: Santiago Iriarte, Ramon Tortosa Navas, Enrique Company Bosch
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Publication number: 20140266314Abstract: A power supply monitoring circuit for monitoring a voltage at a power supply node compared to a reference node, the power supply monitoring circuit comprising a first field effect transistor and first and second voltage dropping components arranged in current flow communication between the power supply node and the reference node and each having first and second nodes, and wherein a first node of the first voltage dropping component is connected to one of the first and second nodes of the field effect transistor, and a gate of the field effect transistor is connected to the second node of the first voltage dropping component, and an output signal is taken from a connection made with the first field effect transistor.Type: ApplicationFiled: March 11, 2014Publication date: September 18, 2014Applicant: Analog Devices TechnologyInventors: Santiago Iriarte, John A. Cleary
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Publication number: 20140253067Abstract: A low drop out voltage regulator comprising: a transistor having an input node, an output node, and a control node; a differential amplifier having an output connected to the control node of the transistor and having a first input node; and a feedback capacitor connected between the output node of the transistor and the first input of the differential amplifier, wherein a voltage at the output of the transistor is dependent on a charge across the feedback capacitor.Type: ApplicationFiled: March 7, 2013Publication date: September 11, 2014Applicant: Analog Devices TechnologyInventors: Ramon Tortosa NAVAS, Enrique COMPANY BOSCH, Santiago IRIARTE
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Publication number: 20140175600Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Applicant: Analog Devices, Inc.Inventors: Alan J. O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin G. LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Publication number: 20140175524Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: February 25, 2014Publication date: June 26, 2014Applicant: ANALOG DEVICES, INC.Inventors: Alan J. O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin G. LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Patent number: 8760216Abstract: A reference voltage generator circuit may include at least one MOS transistor and at least one bipolar transistor coupled together to provide an electrical path from an input reference potential to an output of the generator circuit. The electrical path may extend through a gate-to-source path of the MOS transistor and further through a base-to-emitter path of the bipolar transistor. The MOS transistor may be biased by a bias current that is proportional to T2ยท?(T), where T represents absolute temperature and ?(T) represents mobility of a MOS transistor in the bias current generator. Optionally, the reference voltage generator may include N MOS and M multiple bipolar transistors (N?1, M?1), and the output reference voltage may be N*VGS+M*VBE as compared to the input reference potential.Type: GrantFiled: April 19, 2010Date of Patent: June 24, 2014Assignee: Analog Devices, Inc.Inventors: Santiago Iriarte, Alberto Marinas, Colm Donovan, Eduardo Martinez
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Publication number: 20140034104Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: September 30, 2013Publication date: February 6, 2014Applicant: Analog Devices, Inc.Inventors: Alan J. O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin G. LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Publication number: 20140035630Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: September 30, 2013Publication date: February 6, 2014Applicant: ANALOG DEVICES, INC.Inventors: Alan J. O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin G. LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Publication number: 20140026649Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: September 30, 2013Publication date: January 30, 2014Applicant: ANALOG DEVICES, INC.Inventors: Alan J. O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin G. LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Patent number: 8569861Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: GrantFiled: December 22, 2010Date of Patent: October 29, 2013Assignee: Analog Devices, Inc.Inventors: Alan O'Donnell, Santiago Iriarte, Mark J. Murphy, Colin Lyden, Gary Casey, Eoin Edward English
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Publication number: 20130050132Abstract: Techniques to control a capacitive touch screen that decrease processing time and increase noise rejection. The techniques may include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen, sampling signals returned from the screen, and determining a location of touch. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto adjacent or non-adjacent conductors of the capacitive touch screen. The techniques may further include injecting a plurality of excitation signals having unique spectral profiles onto conductors of the capacitive touch screen in unequal measures. The techniques may also include mapping frequency characteristics of noise present on the capacitive touch screen.Type: ApplicationFiled: August 26, 2011Publication date: February 28, 2013Applicant: ANALOG DEVICES, INC.Inventors: Javier Calpe Maravilla, Alberto Marinas, Santiago Iriarte, Enrique Company Bosch, Miguel Chanca, Reza Alavi, Vladimir Friedman, John Cleary
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Patent number: 8373459Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: GrantFiled: January 12, 2011Date of Patent: February 12, 2013Assignee: Texas Instruments IncorporatedInventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Patent number: 8330505Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.Type: GrantFiled: March 31, 2011Date of Patent: December 11, 2012Assignee: Analog Devices, Inc.Inventors: Santiago Iriarte, Alberto Marinas, Colm Donovan, Eduardo Martinez
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Publication number: 20120286833Abstract: An integrated circuit provides a power on reset signal with respect to a supply voltage level supplying the electronic device. The integrated circuit comprises a bias current generating stage having a first current mirror and an output stage having first, second and third series connected MOS transistors. A connection between the second MOS transistor and the third MOS transistor forms a POR output node. A gate of the second MOS transistor and a gate of the third MOS transistor are coupled to each other and to the first current mirror. This allows a current through the third MOS transistor when the supply voltage is higher than a first MOS transistor threshold and a current through the second MOS transistor only when the supply voltage is greater than or equal to the sum of the first MOS transistor threshold and a second MOS transistor threshold voltage.Type: ApplicationFiled: January 12, 2011Publication date: November 15, 2012Applicant: TEXAS INSTRUMENTS INCORPORATEDInventors: Santiago Iriarte Garcia, Johannes Gerber, Bernhard Wolfgang Ruck
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Publication number: 20120249185Abstract: A detection circuit is coupled to an output terminal of a driver circuit. The detection circuit includes a comparator to compare a signal at the output terminal to a reference signal corresponding to a signal that would be generated if a capacitive load having a relatively high capacitance value were connected to the output terminal. Output of the comparator is sampled at a predetermined time after the driver circuit provides the drive signal. An error signal is generated when the sampled output indicates that the capacitive load having the relatively high capacitance value is actually connected to the output terminal.Type: ApplicationFiled: March 31, 2011Publication date: October 4, 2012Applicant: ANALOG DEVICES, INC.Inventors: Santiago Iriarte, Alberto Marinas, Colm Donovan, Eduardo Martinez
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Publication number: 20120229264Abstract: The present invention provides a haptics control system that may include a driver to generate a continuous drive signal and to output the drive signal to a mechanical system on an electrical signal line, wherein the continuous drive signal causes the mechanical system to vibrate to produce a haptic effect. The haptics control system may further include a monitor, coupled to the electrical signal line, to capture a Back Electromotive Force (BEMF) signal generated by the mechanical system in the electrical signal line, to measure a BEMF signals attribute, and to transmit an adjustment signal to the driver based on the BEMF signals attribute. The driver is further configured to adjust the continuous drive signal according to the adjustment signal.Type: ApplicationFiled: August 26, 2011Publication date: September 13, 2012Applicant: ANALOG DEVICES, INC.Inventors: Enrique Company Bosch, Javier Calpe Maravilla, Santiago Iriarte, Eoghan Moloney, Krystian Balicki, Mark Murphy, Eoin Edward English, Pedro Lopez Canovas
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Publication number: 20120223688Abstract: A low dropout voltage regulator (LDO) includes first and second amplifiers and a current mirror. The first amplifier includes a first input receiving a reference voltage and a second input receiving a voltage proportional to an output of the LDO. The current mirror includes an input current at a first end of the current mirror to an output current at a second end of the current mirror, the input current controlled by an output of the first amplifier and the output current being supplied to the output of the LDO. The second amplifier includes a first input coupled to the first end of the current mirror and a second input coupled to the second end of the current mirror.Type: ApplicationFiled: May 20, 2011Publication date: September 6, 2012Applicant: ANALOG DEVICES, INC.Inventors: Santiago IRIARTE, Alberto MARINAS
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Patent number: 8212617Abstract: A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.Type: GrantFiled: January 5, 2010Date of Patent: July 3, 2012Assignee: Analog Devices, Inc.Inventors: Alberto Marinas, Santiago Iriarte, Colm Donovan, Eduardo Martinez
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Publication number: 20120162947Abstract: Embodiments of the present invention provide an integrated circuit system including a first active layer fabricated on a front side of a semiconductor die and a second pre-fabricated layer on a back side of the semiconductor die and having electrical components embodied therein, wherein the electrical components include at least one discrete passive component. The integrated circuit system also includes at least one electrical path coupling the first active layer and the second pre-fabricated layer.Type: ApplicationFiled: December 22, 2010Publication date: June 28, 2012Applicant: ANALOG DEVICES, INC.Inventors: Alan O'DONNELL, Santiago IRIARTE, Mark J. MURPHY, Colin LYDEN, Gary CASEY, Eoin Edward ENGLISH
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Publication number: 20110163811Abstract: A system for a Class AB Amplifier output stage that includes a first push pull system connected to an output terminal including a first driving transistor coupled to the output terminal and a second push pull system connected to the output terminal including a second driving transistor coupled to the output terminal. The amplifier also includes a current mode amplifier where the current mode amplifier's output is coupled to the first driving transistor's gate. The amplifier further includes a pair of resistors, a first resistor coupled to a first input terminal of the current mode amplifier, a second resistor coupled to a second input terminal of the current mode amplifier and coupled to the second driving transistor.Type: ApplicationFiled: January 5, 2010Publication date: July 7, 2011Applicant: ANALOG DEVICES, INC.Inventors: Alberto MARINAS, Santiago IRIARTE, Colm DONOVAN, Eduardo MARTINEZ