Patents by Inventor Sapumal Wijeratne
Sapumal Wijeratne has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11275663Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).Type: GrantFiled: June 8, 2020Date of Patent: March 15, 2022Assignee: Intel CorporationInventors: Alexander Gendler, Nimrod Angel, Ameya Ambardekar, Sapumal Wijeratne, Vikas Vij, Tod Schiff, Alexander Uan-Zo-Li
-
Publication number: 20210382805Abstract: A dedicated pin of a processor or system-on-chip (SoC) is used to indicate whether power level (e.g., charge, voltage, and/or current) of a battery falls below a threshold. The threshold can be predetermined or programmable. The battery is used to provide power to the processor and/or SoC. Upon determining that the power level of the battery falls below the threshold, the processor by-passes the conventional process of entering low performance or power mode, and directly throttles voltage and/or operating frequency of the processor. This allows the processor to continue to operate at low battery power. The fast transition (e.g., approximately 10 ?S) from an active state to a low performance or power mode, in accordance with a logic level of the voltage on the dedicated pin, reduces decoupling capacitor design requirements, and makes it possible for the processor to adapt higher package power control settings (e.g., PL4).Type: ApplicationFiled: June 8, 2020Publication date: December 9, 2021Applicant: Intel CorporationInventors: Alexander Gendler, Nimrod Angel, Ameya Ambardekar, Sapumal Wijeratne, Vikas Vij, Tod Schiff, Alexander Uan-Zo-Li
-
Patent number: 7656702Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.Type: GrantFiled: December 31, 2007Date of Patent: February 2, 2010Assignee: Intel CorporationInventors: Sapumal Wijeratne, Matthew W. Ernest, Brian A. Kuns
-
Publication number: 20090168509Abstract: Methods and apparatus to provide ultra low voltage, low leakage, high density, and/or variation tolerant memory bit cells are described. In one embodiment, each of the cross-coupled invertors of a memory cell may include a plurality of p-channel transistors. Other embodiments are also described.Type: ApplicationFiled: December 31, 2007Publication date: July 2, 2009Inventors: Sapumal Wijeratne, Matthew W. Ernest, Brian A. Kuns
-
Patent number: 7516173Abstract: A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.Type: GrantFiled: August 4, 2004Date of Patent: April 7, 2009Assignee: Intel CorporationInventor: Sapumal Wijeratne
-
Publication number: 20090086556Abstract: A low voltage memory apparatus is disclosed. The memory apparatus can include a bit cell, a first pass gate coupled to the bit cell to receive a write signal, a second pass gate coupled to the bit cell to receive the write signal, and a bit cell isolator to isolate at least a portion of the bit cell from a power return during a write cycle. Isolating a cross coupled flip flop in the bit cell during a write cycle can provide faster write times, increased write reliability and can reduce the effects of device variations on bit cell operation, particularly for low voltage applications. Other embodiments are also disclosed.Type: ApplicationFiled: September 27, 2007Publication date: April 2, 2009Inventors: Sapumal Wijeratne, Jeff Miller
-
Patent number: 7509368Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.Type: GrantFiled: May 9, 2005Date of Patent: March 24, 2009Assignee: Intel CorporationInventors: Mark A. Anders, Sanu K. Mathew, Nanda Siddaiah, Sapumal Wijeratne
-
Patent number: 7325024Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.Type: GrantFiled: December 4, 2003Date of Patent: January 29, 2008Assignee: Intel CorporationInventors: Sanu K. Mathew, Mark A. Anders, Ram K. Krishnamurthy, Sapumal Wijeratne
-
Patent number: 7202703Abstract: A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.Type: GrantFiled: January 30, 2004Date of Patent: April 10, 2007Assignee: Intel CorporationInventor: Sapumal Wijeratne
-
Patent number: 7161389Abstract: A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.Type: GrantFiled: June 30, 2004Date of Patent: January 9, 2007Assignee: Intel CorporationInventors: Sapumal Wijeratne, Daniel J. Deleganes
-
Publication number: 20060253523Abstract: An adder circuit is provided that includes a propagate and generate circuit stage to provide propagate and generate signals, a plurality of carry-merge stages to provide carry signals based on the propagate and generate signals and a conditional sum generator to provide conditional sums based on the propagate and generate signals. The conditional sum generator includes ripple carry gates and XOR logic gates. The adder circuit also includes a plurality of multiplexers to receive the carry signals and the conditional sums and to provide an output based on the input signals.Type: ApplicationFiled: May 9, 2005Publication date: November 9, 2006Inventors: Mark Anders, Sanu Mathew, Nanda Siddaiah, Sapumal Wijeratne
-
Patent number: 7002855Abstract: A register file includes a dynamic local bit trace, a plurality of data cells coupled to the dynamic local bit trace, and a device coupled to the dynamic local bit trace to facilitate precharging the dynamic local bit trace to a precharge value and to intelligently hold the precharged value on the dynamic local bit trace during evaluation of the dynamic local bit trace.Type: GrantFiled: January 30, 2004Date of Patent: February 21, 2006Assignee: Intel CorporationInventors: Sapumal Wijeratne, Pankaj Aswal, Mohammad M. Haq, Marijan Persun
-
Publication number: 20060031280Abstract: A multi-bit adder includes a carry chain, a carry-skip network, sum cells, and a carry-sum cell. The carry chain propagates, generates, or kills carry-in bits. The carry-skip network is coupled to the carry chain to selectively skip the carry-in bits over at least one portion of the carry chain. The sum cells are coupled along the carry chain to sum the carry-in bits with corresponding bits of two operands to generate a multi-bit resultant. The carry-sum cell is coupled to receive one of the carry-in bits to a single intermediate bit position on the carry chain and to generate one bit of the multi-bit resultant having a more significant bit position than the single intermediate bit position.Type: ApplicationFiled: August 4, 2004Publication date: February 9, 2006Inventor: Sapumal Wijeratne
-
Publication number: 20060001452Abstract: A ratioed logic gate includes a contention interrupt circuit. The ratioed logic gate includes a pull up network coupled to a pull down network. Multiple inputs are coupled to turn the pull down and pull up networks on and off. An output is coupled to apply a logical function on the multiple inputs. A contention interrupt circuit is coupled to one of the pull up and the pull down networks to open circuit the one of the pull up and pull down networks when the pull up and pull down networks are in contention.Type: ApplicationFiled: June 30, 2004Publication date: January 5, 2006Inventors: Sapumal Wijeratne, Daniel Deleganes
-
Patent number: 6958629Abstract: A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.Type: GrantFiled: January 30, 2004Date of Patent: October 25, 2005Assignee: Intel CorporationInventor: Sapumal Wijeratne
-
Publication number: 20050169074Abstract: A circuit comprises an evaluate clock trace to receive an evaluate clock signal and a precharge clock trace to receive a precharge clock signal. The circuit further comprises sample circuitry coupled to a first signal trace, a second signal trace, the precharge clock trace and the evaluate clock trace to facilitate a detection of a transition on the first signal trace from a first voltage level to a second voltage level. In addition, the circuit comprises latch circuitry coupled to the first signal trace, the second signal trace, the precharge clock trace and the evaluate clock trace to utilize at least a portion of the sample circuitry to maintain voltage levels on the first and the second signal traces when an evaluate clock and a precharge clock are inactive.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Inventor: Sapumal Wijeratne
-
Publication number: 20050168244Abstract: A circuit comprises a signal trace to receive a first large signal, a first plurality of signal traces to receive a small signal pair and a clock trace to receive a clock signal. The circuit further comprises a mixed signal circuit having at least a first and a second element, coupled to the signal trace, the first plurality of signal traces and the clock trace. The mixed signal circuit it to facilitate generation of a second large signal based at least in part on the small signal pair and the first large signal, with the first large signal and the clock signal driving the first and second elements respectively to transition asynchronously.Type: ApplicationFiled: January 30, 2004Publication date: August 4, 2005Inventor: Sapumal Wijeratne
-
Patent number: 6922082Abstract: An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.Type: GrantFiled: September 30, 2003Date of Patent: July 26, 2005Assignee: Intel CorporationInventor: Sapumal Wijeratne
-
Publication number: 20050125481Abstract: An adder circuit includes a number of selectors and an adder. The selectors feed the adder with multiple input data bits. Each of the selectors includes a combination of a multiplexing network and a sense amplifier to select from a number of input values to generate the multiple input data bits. The combination of the multiplexing network and the sense amplifier acts as the state-holding element at the input of the adder, avoiding the overheads of an explicit latch stage.Type: ApplicationFiled: December 4, 2003Publication date: June 9, 2005Inventors: Sanu Mathew, Mark Anders, Ram Krishnamurthy, Sapumal Wijeratne
-
Publication number: 20050068065Abstract: An apparatus comprising a low voltage swing (LVS) circuit having a plurality of alternating LVS pre-charging and evaluation phases and a select logic circuit coupled to the LVS circuit and responsive to a plurality of input data signals to generate a plurality of select signals for the LVS circuit. Each of the select signals occurs during one of the LVS evaluation phases and has a turning-on edge and a turning-off edge. The turning-off edge of each of the select signals is generated independent of the input data signals.Type: ApplicationFiled: September 30, 2003Publication date: March 31, 2005Inventor: Sapumal Wijeratne