Abstract: A semiconductor memory device including: first and second memory cells storing multi-bit data; a first word line coupled to the first memory cell; and a second word line connected to the second memory cell and adjacent to the first word line; wherein a period in which a first word line voltage for reading data stored in the first memory cell is applied includes: a first period in which a first voltage level is applied to read first bit data from the multi-bit data stored in the first memory cell; a second period having a second voltage level lower than the first voltage level; and a third period in which a third voltage level higher than the second voltage level is applied to read second bit data from the multi-bit data stored in the first memory cell, wherein in the second period, the second word line is in a floating state.

Abstract: Aspects disclosed in the detailed description include offset-canceling (OC) write operation sensing circuits for sensing switching in a magneto-resistive random access memory (MRAM) bit cell in an MRAM for a write operation. The OC write operation sensing circuit is configured to sense when MTJ switching occurs in MRAM bit cell. In an example, the OC write operation sensing circuit includes a voltage sensing circuit and a sense amplifier. The voltage sensing circuit employs a capacitive-coupling effect so that the output voltage drops in response to MTJ switching for both logic ‘0’ and logic ‘1’ write operations. The sense amplifier has a single input and a single output node with an output voltage indicating when MTJ switching has occurred in the MRAM bit cell. A single input transistor and pull-up transistor are provided in the sense amplifier in one example to provide an offset-canceling effect.

Abstract: In an embodiment, an error detection and correction apparatus includes a positive edge triggered flip-flop that receives syndrome input based on a syndrome output a syndrome generator indicating whether or not input data includes an error, whereby the positive edge triggered flip-flop further provides a syndrome output to an error location decoder.

Abstract: Sensing voltage based on a supplied to magneto-resistive random access memory (MRAM) bit cells in an MRAM for tracking write operations. Sensing voltage based on supply voltage applied to an MRAM bit cell in a write operation can be used to detect completion of magnetic tunnel junction (MTJ) switching in an MRAM bit cell to terminate the write operation to reduce power and write times. In exemplary aspects provided herein, reference and write operation voltages sensed from the MRAM bit cell in response to the write operation are compared to each other to detect completion of MTJ switching of voltage based on the supply voltage applied to the MRAM bit cell regardless of whether the write operation is logic ‘0’ or logic ‘1’ write operation. This provides a higher sensing margin, because the change in MTJ resistance after MTJ switching completion is larger at the supply voltage rail.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Error detection and correction decoding apparatus performs single error correction-double error detection (SEC-DED) or double error correction-triple error detection (DEC-TED) depending on whether the data input contains a single-bit error or a multiple-bit error, to reduce power consumption and latency in case of single-bit errors and to provide powerful error correction in case of multiple-bit errors.

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.

Abstract: Systems and methods relate to providing a constant sensing current for reading a resistive memory element. A load voltage generator provides a load voltage based on a current mirror configured to supply a constant current that is invariant with process-voltage-temperature variations. A data voltage is generated based on the generated load voltage, by passing a sensing current mirrored from the constant current, through the resistive memory element. A reference voltage is generated, also based on the generated load voltage and by passing reference current mirrored from the constant current, through reference cells. A logical value stored in the resistive memory element is determined based on a comparison of the data voltage and the reference voltage, where the determination is free from effects of process-voltage-temperature variations.