Patents by Inventor Sarah L. Lane
Sarah L. Lane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8120143Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.Type: GrantFiled: February 21, 2008Date of Patent: February 21, 2012Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
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Patent number: 7998880Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: GrantFiled: July 30, 2007Date of Patent: August 16, 2011Assignees: International Business Machines Corporation, Sony CorporationInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Publication number: 20100028695Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: ApplicationFiled: July 30, 2007Publication date: February 4, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Patent number: 7585722Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.Type: GrantFiled: January 10, 2006Date of Patent: September 8, 2009Assignee: International Business Machines CorporationInventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
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Patent number: 7494938Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: GrantFiled: February 5, 2007Date of Patent: February 24, 2009Assignees: International Business Machines Corporation, Sony Corporation, Sony Electronics Inc.Inventors: Son V. Nguyen, Sarah L. Lane, Jia Lee, Kensaku Ida, Darryl D. Restaino, Takeshi Nogami
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Publication number: 20080130200Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.Type: ApplicationFiled: February 21, 2008Publication date: June 5, 2008Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
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Patent number: 7265437Abstract: A low k dielectric stack having an effective dielectric constant k, of about 3.0 or less, in which the mechanical properties of the stack are improved by introducing at least one nanolayer into the dielectric stack. The improvement in mechanical properties is achieved without significantly increasing the dielectric constant of the films within the stack and without the need of subjecting the inventive dielectric stack to any post treatment steps. Specifically, the present invention provides a low k dielectric stack that comprises at least one low k dielectric material and at least one nanolayer present within the at least one low k dielectric material.Type: GrantFiled: March 8, 2005Date of Patent: September 4, 2007Assignees: International Business Machines Corporation, Sony CorporationInventors: Son V. Nguyen, Sarah L. Lane, Eric G. Liniger, Kensaku Ida, Darryl D. Restaino
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Publication number: 20070158717Abstract: The invention is directed to an integrated circuit comb capacitor with capacitor electrodes that have an increased capacitance between neighboring capacitor electrodes as compared with other interconnects and via contacts formed in the same metal wiring level and at the same pitches. The invention achieves a capacitor that minimizes capacitance tolerance and preserves symmetry in parasitic electrode-substrate capacitive coupling, without adversely affecting other interconnects and via contacts formed in the same wiring level, through the use of, at most, one additional noncritical, photomask.Type: ApplicationFiled: January 10, 2006Publication date: July 12, 2007Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel C. Edelstein, Anil K. Chinthakindi, Timothy J. Dalton, Ebenezer E. Eshun, Jeffrey P. Gambino, Sarah L. Lane, Anthony K. Stamper
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Patent number: 7202564Abstract: A porous low k or ultra low k dielectric film comprising atoms of Si, C, O and H (hereinafter “SiCOH”) in a covalently bonded tri-dimensional network structure having a dielectric constant of less than about 3.0, a higher degree of crystalline bonding interactions, more carbon as methyl termination groups and fewer methylene, —CH2— crosslinking groups than prior art SiCOH dielectrics is provided. The SiCOH dielectric is characterized as having a FTIR spectrum comprising a peak area for CH3+CH2 stretching of less than about 1.40, a peak area for SiH stretching of less than about 0.20, a peak area for SiCH3 bonding of greater than about 2.0, and a peak area for Si—O—Si bonding of greater than about 60%, and a porosity of greater than about 20%.Type: GrantFiled: February 16, 2005Date of Patent: April 10, 2007Assignee: International Business Machines CorporationInventors: Son Nguyen, Sarah L. Lane, Jia Lee, Kensaku Ida, Darryl D. Restaino, Takeshi Nogami
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Patent number: 6939797Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: GrantFiled: November 12, 2003Date of Patent: September 6, 2005Assignee: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino
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Publication number: 20040173908Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: ApplicationFiled: November 12, 2003Publication date: September 9, 2004Inventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino
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Patent number: 6737747Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: GrantFiled: January 15, 2002Date of Patent: May 18, 2004Assignee: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino
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Publication number: 20030132510Abstract: An advanced back-end-of-line (BEOL) metallization structure is disclosed. The structure includes a diffusion barrier or cap layer having a low dielectric constant (low-k), where the cap layer is formed of silicon nitride by a plasma-enhanced chemical vapor deposition (PE CVD) process. The metallization structure also includes an inter-layer dielectric (ILD) formed of a carbon-containing dielectric material having a dielectric constant of less than about 4, and a continuous hardmask layer overlying the ILD which is preferably formed of silicon nitride or silicon carbide. A method for forming the BEOL metallization structure is also disclosed. The method includes a pre-clean or pre-activation step to improve the adhesion of the cap layer to the underlying copper conductors. The pre-clean or pre-activation step comprises exposing the copper surface to a reducing plasma including hydrogen, ammonia, nitrogen and/or noble gases.Type: ApplicationFiled: January 15, 2002Publication date: July 17, 2003Applicant: International Business Machines CorporationInventors: Edward Barth, John A. Fitzsimmons, Stephen M. Gates, Thomas H. Ivers, Sarah L. Lane, Jia Lee, Ann McDonald, Vincent McGahay, Darryl D. Restaino