Patents by Inventor Saratchandar Adayapalam VISWANATHAN

Saratchandar Adayapalam VISWANATHAN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10797824
    Abstract: Methods, nodes and control modules are disclosed. In the method, circuitry of a first node in a mesh network converts an optical layer in a working path between the first node and a second node, to a data stream in a digital layer. The working path carries data traffic from the first node to the second node in the optical layer of the mesh network when there is no failure in the working path. Circuitry of the first node in the mesh network detects a failure in the working path due to detection of an error in the data stream in the digital layer. The circuitry of the first node establishes, through transmission of at least one signal from the first node to the second node, a restoration path in the optical layer based on, at least in part, detection of the error in the data stream in the digital layer.
    Type: Grant
    Filed: June 5, 2018
    Date of Patent: October 6, 2020
    Assignee: Infinera Corporation
    Inventors: Rajan Rao, Ashok Kunjidhapatham, Ashwini Kumar Bhat, Baranidhar Ramanathan, Sanjeev Ramachandran, Nikhil Satyarhi, Saratchandar Adayapalam Viswanathan, Biao Lu, Amit Satbhaiya, Ramnarayan Srinivasan, Ramakrishna Pratapa
  • Publication number: 20180351694
    Abstract: Methods, nodes and control modules are disclosed. In the method, circuitry of a first node in a mesh network converts an optical layer in a working path between the first node and a second node, to a data stream in a digital layer. The working path carries data traffic from the first node to the second node in the optical layer of the mesh network when there is no failure in the working path. Circuitry of the first node in the mesh network detects a failure in the working path due to detection of an error in the data stream in the digital layer. The circuitry of the first node establishes, through transmission of at least one signal from the first node to the second node, a restoration path in the optical layer based on, at least in part, detection of the error in the data stream in the digital layer.
    Type: Application
    Filed: June 5, 2018
    Publication date: December 6, 2018
    Inventors: Rajan Rao, Ashok Kunjidhapatham, Ashwini Kumar Bhat, Baranidhar Ramanathan, Sanjeev Ramachandran, Nikhil Satyarhi, Saratchandar Adayapalam Viswanathan, Biao Lu
  • Patent number: 10075259
    Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.
    Type: Grant
    Filed: April 8, 2016
    Date of Patent: September 11, 2018
    Assignee: Infinera Corporation
    Inventors: Saurabh Pandey, Saratchandar Adayapalam Viswanathan, Vinay Khana
  • Publication number: 20170195080
    Abstract: Systems and methods for time slot allocation of time slots for bundled links in a shared mesh GMPLS for protect paths with different of COS may include time slot allocation divided into multiple phases with each phase having some qualification criterion to go to next phase or exit if the criterion is not met. For example, allocation of time slots for a circuit may include three phases—component selection phase, a connection admission phase, and an optimization phase.
    Type: Application
    Filed: April 8, 2016
    Publication date: July 6, 2017
    Inventors: Saurabh PANDEY, Saratchandar Adayapalam VISWANATHAN, Vinay KHANA