Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A programmable logic device (PLD) includes a non-volatile memory, a configuration memory, and a control circuitry. The control circuitry couples to the non-volatile memory and to the configuration memory. A set of voltages are derived from the outputs of the control circuitry, and are applied to circuitry within the PLD.

Abstract: An apparatus for compensating for glitch occurrence in a reset signal that is applied in an integrated circuit, includes: a logic stage capable to process an incoming signal and a delayed incoming signal that is a delayed version of the incoming signal, the logic stage capable to generate an output signal so that when the incoming signal and the delayed incoming signal are in the same state, the output signal will be in the same state.

Abstract: A word line block, a data block and at least one memory cell form a memory architecture and impose no special timing requirements to handle the synchronization of the outputs of the word line block with the data block. Further, the word line block contains a transmitting transistor and the data block contains a functionally similar transmitting transistor. These transmitting transistors responsive to a write enable signal and a clock signal synchronize a selection signal supplied to the memory cell when data is also supplied to the memory cell. Furthermore, a place in route tool can automatically place and route the word line block, the data block and the at least one memory cell based on chip requirements. Also, with the clock signal proximate the output of the word line block and data block, the place and route tool is able to automatically place and route the blocks and the at least one memory cell to compensate for any calculated interconnection delays.

Abstract: The present invention provides a buffer for coupling circuitry operating at a low voltage to circuitry operating a high voltage, and vice versa. The buffer outputs signals in a range between the low voltage and a ground voltage lower than the low voltage, and maintains appropriate bias of a semiconductor junction in the buffer using the high voltage. For example, the high voltage can be applied to the body of an output stage pull-up PFET of the buffer to maintain reverse bias between the body and drain of the PFET even when signals at the high voltage are placed on the drain of the PFET by other circuitry. Some embodiments of the present invention include a voltage translator to translate signals output from circuitry operating at the low voltage into a control signal at either the ground voltage or the high voltage. The high voltage of the control signal is beneficial for turning OFF an output stage transistor of the buffer even in the presence of signals at the high voltage on an output of the buffer.

Abstract: A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit.

Abstract: A voltage tolerant input/output buffer comprises a current mirror, a voltage sensing and isolating circuit, an output pull-up transistor, and an output pull-down transistor. The output pull-up transistor preferably has its gate coupled to the voltage sensing and isolating circuit to receive signals from the lower voltage circuitry, its source coupled to the supply voltage for the lower operating voltage circuitry, and its drain provides the output for connection to the higher voltage circuitry. The voltage sensing and isolating circuit is coupled between the gate and the drain of the output pull-up transistor. The current mirror is coupled to ground and to the voltage sensing and isolating circuit. The output pull-down transistor has its drain coupled to the voltage sensing and isolating circuit, it source coupled to ground, and its gate coupled to receive pull down signals from the lower operating voltage circuit.

Abstract: A voltage tolerant bus hold latch comprises a first buffer transistor, a sense transistor, a low voltage latch, a node voltage controller and a pull-up circuit. The low voltage latch is coupled to the input by the first transistor. The node voltage controller is coupled to the input by the sense transistor. The node voltage controller has a pair of additional inputs coupled to the output of the low voltage latch. The output of the node voltage controller is coupled to control the operation of the pull-up circuit. The pull-up circuit is coupled to the supply voltage for the lower voltage circuitry, and has another control input coupled to the output of the low voltage latch. The output of the pull-up circuit is coupled to the input of the voltage tolerant latch. The pull-up circuit is selectively activated to pull the input of the latch to a high voltage level.